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| this is information on a product in full production. april 2017 docid028094 rev 5 1/142 stm32f410x8 stm32f410xb arm ? -cortex ? -m4 32b mcu+fpu, 125 dmips, 128kb flash, 32kb ram, 9 tims, 1 adc, 1 da c, 1 lptim, 9 comm. interfaces datasheet - production data features ? dynamic efficiency line with ebam (enhanced batch acquisition mode) ? 1.7 v to 3.6 v power supply ? -40 c to 85/105/125 c temperature range ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 100 mhz, memory protection unit, 125 dmips/1.25 dmips/ mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 128 kbytes of flash memory ? 512 bytes of otp memory ? 32 kbytes of sram ? clock, reset and supply management ? 1.7 v to 3.6 v applic ation supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? power consumption ? run: 89 a/mhz (peripheral off) ? stop (flash in stop mode, fast wakeup time): 40 a typ @ 25 c; 49 a max @25 c ? stop (flash in deep power down mode, slow wakeup time): down to 6 a @ 25 c; 14 a max @25 c ? standby: 2.4 a @25 c / 1.7 v without rtc; 12 a @85 c @1.7 v ?v bat supply for rtc: 1 a @25 c ? 112-bit, 2.4 msps adc: up to 16 channels ? 112-bit d/a converter ? general-purpose dma: 16-stream dma controllers with fifos and burst support ? up to 9 timers ? one low-power timer (available in stop mode) ? one 16-bit advanced motor-control timer ? three 16-bit general purpose timers ? one 32-bit timer up to 100 mhz with up to four ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? two watchdog timers (independent window) ? systick timer. ? debug mode ? serial wire debug (swd) & jtag interfaces ?cortex ? -m4 embedded trace macrocell? ? up to 50 i/o ports wit h interrupt capability ? up to 45 fast i/os up to 100 mhz ? up to 49 5 v-tolerant i/os ? up to 9 communication interfaces ? up to 3x i 2 c interfaces (smbus/pmbus) including 1x i 2 c fast-mode at 1 mhz ? up to 3 usarts (2 x 12.5 mbit/s, 1 x 6.25 mbit/s), iso 7816 interface, lin, irda, modem control) ? up to 3 spi/i2ss (up to 50 mbit/s spi or i2s audio protocol) ? true random number generator ? crc calculation unit ? 96-bit unique id ? rtc: subsecond accuracy, hardware calendar ? all packages are ecopack ? 2 table 1. device summary reference part number stm32f410x8 STM32F410T8, stm32f410c8, stm32f410r8 stm32f410xb stm32f410tb, stm32f410cb, stm32f410rb wlcsp36 ufqfpn48 (77mm) (2.553x2.579mm) lqfp48 (7x7mm) & " ' ! ufbga64 ( 5x5mm ) lqfp64 (1010mm) www.st.com
contents stm32f410x8/b 2/142 docid028094 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 compatibility with stm32f4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram . . . 16 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 16 3.3 batch acquisition mode (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 17 3.7 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.1 internal power supp ly supervisor availability . . . . . . . . . . . . . . . . . . . . . 22 3.17 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.19 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20.1 advanced-control timers (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20.2 general-purpose timers (tim5, tim9 and tim11) . . . . . . . . . . . . . . . . . 26 3.20.3 basic timer (tim6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 docid028094 rev 5 3/142 stm32f410x8/b contents 5 3.20.4 low-power timer (lptim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.5 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.6 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.21 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.22 universal synchronous/asynchronous re ceiver transmitters (usart) . . 28 3.23 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.24 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.25 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.27 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.28 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.29 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.30 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.31 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.2 vcap_1 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.3 operating conditions at power-up/power-down (regulator on) . . . . . . . 56 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 56 6.3.5 embedded reset and power control bloc k characteristics . . . . . . . . . . . 57 contents stm32f410x8/b 4/142 docid028094 rev 5 6.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.7 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.9 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.11 pll spread spectrum clock generatio n (sscg) characteristics . . . . . . 86 6.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 91 6.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.24 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.25 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 wlcsp36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.2 ufqfpn48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.4 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.5 ufbga64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.6.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 appendix a recommendations wh en using the internal reset off . . . . . . . . 137 a.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 appendix b application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 b.1 sensor hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 docid028094 rev 5 5/142 stm32f410x8/b contents 5 b.2 batch acquisition mode (bam) example . . . . . . . . . . . . . . . . . . . . . . . . . 139 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 list of tables stm32f410x8/b 6/142 docid028094 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f410x8/b features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. regulator on/off and internal power supply superv isor availability. . . . . . . . . . . . . . . . . 22 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. stm32f410x8/b pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. stm32f410x8/b register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 15. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16. features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 55 table 17. vcap_1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 18. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 56 table 19. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 56 table 20. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 1.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 22. typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - v dd = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except pr efetch) running from flash memory- v dd = 1.7 v . . . 61 table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except pref etch) running from flash memory - v dd = 3.6 v . . 62 table 25. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 3.6 v. . . . . . . . . . . . . . . 63 table 26. typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 1.7 v. . . . . . . . . . . . . . . 64 table 27. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory - v dd = 3.6 v . . . . . 65 table 28. typical and maximum current consumption in sleep mode - v dd = 3.6 v . . . . . . . . . . . . . 66 table 29. typical and maximum current consumption in sleep mode - v dd = 1.7 v . . . . . . . . . . . . . 68 table 30. typical and maximum current consumptions in stop mode - v dd = 1.7 v . . . . . . . . . . . . . 70 table 31. typical and maximum current consumption in stop mode - v dd =3.6 v. . . . . . . . . . . . . . . 70 table 32. typical and maximum current consumption in standby mode - v dd = 1.7 v . . . . . . . . . . . 70 table 33. typical and maximum current consumption in standby mode - v dd = 3.6 v . . . . . . . . . . . 71 table 34. typical and maximum current consumptions in v bat mode (lse and rtc on, lse low- drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 35. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 37. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 40. hse 4-26 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 docid028094 rev 5 7/142 stm32f410x8/b list of tables 8 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 42. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 44. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 45. sscg parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 46. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 47. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 48. flash memory programming with v pp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 49. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 50. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 51. emi characteristics for lqfp64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 52. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 53. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 54. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 55. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 56. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 57. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 58. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 59. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 60. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 61. scl frequency (f pclk1 = 50 mhz, v dd = v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . 100 table 62. scl frequency (f pclk1 = 42 mhz.,v dd = v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. fmpi 2 c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 65. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 66. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 67. adc accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 68. adc accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 69. adc accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 70. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 111 table 71. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 111 table 72. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 table 73. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 74. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 75. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 76. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 77. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 78. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 79. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 80. wlcsp36 recommended pcb design rules (0.4 mm pi tch) . . . . . . . . . . . . . . . . . . . . . . 121 table 81. ufqfpn48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 82. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 83. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data. . . . . . . . . 130 table 84. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pi tch ultra profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 85. ufbga64 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . . 133 table 86. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 87. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 88. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 137 list of tables stm32f410x8/b 8/142 docid028094 rev 5 table 89. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 docid028094 rev 5 9/142 stm32f410x8/b list of figures 10 list of figures figure 1. compatible board design for lqfp64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. stm32f410x8/b block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 3. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 21 figure 5. lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. ufqfpn48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. ufbga64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. wlcsp36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 10. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 11. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12. input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 16. typical v bat current consumption (lse and rtc on/lse oscillator in ?low power? mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 17. typical v bat current consumption (lse and rtc on/lse oscillator in ?high-drive? mode selectio n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 18. low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 19. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 20. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 21. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 22. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 23. acc hsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 24. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 25. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 26. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 27. ft/tc i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 28. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 29. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 31. fmpi 2 c timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 32. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 33. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 34. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 35. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 36. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 37. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 38. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 39. power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 40. 12-bit buffered/non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 41. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 42. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 43. wlcsp36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 44. ufqfpn48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat list of figures stm32f410x8/b 10/142 docid028094 rev 5 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 45. ufqfpn48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 46. ufqfpn48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 47. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 125 figure 48. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 49. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 50. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 129 figure 51. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0 figure 52. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 53. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 54. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 55. ufbga64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 56. sensor hub application example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 57. sensor hub application example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 58. batch acquisition mode (bam) example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 docid028094 rev 5 11/142 stm32f410x8/b introduction 31 1 introduction this datasheet provides the descriptio n of the stm32f410x8/b microcontrollers. for information on the cortex ? -m4 core, please refer to the cortex ? -m4 programming manual (pm0214) available from www.st.com . description stm32f410x8/b 12/142 docid028094 rev 5 2 description the stm32f410 x 8/b devices are based on the high-performance arm ? cortex ? -m4 32- bit risc core operating at a frequency of up to 100 mhz. their cortex ? -m4 core features a floating point unit (fpu) single precision which supports all arm single-precision data- processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f410 x 8/b belong to the stm32 dynamic efficiency ? product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called batch acquisition mode (bam) allowing to sa ve even more power consumption during data batching. the stm32f410 x 8/b incorporate high-speed embedded memories (up to 128 kbytes of flash memory, 32 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to tw o apb buses, one ahb bus and a 32-bit multi-ah b bus matrix. all devices offer one 12-bit adc, one 12-bit dac, a low-power rtc, three general-purpose 16-bit timers, one pwm timer for motor control, one general-purpose 32-bit timers and one 16-bit low-power timer. they also feature standard and advanced communication interfaces. ? up to three i 2 cs ? three spis ? three i 2 ss to achieve audio class accuracy, the i 2 s peripherals can be clocked via the internal pll or via an external clo ck to allow synchronization. ? three usarts. the stm32f410x8/b are offered in 5 packages ranging from 36 to 64 pins. the set of available peripherals depends on the selected package. refer to table 2: stm32f410x8/b features and peripheral counts for the peripherals available for each part number. the stm32f410x8/b operate in the ? 40 to +125 c temperature range from a 1.7 (pdr off) to 3.6 v power supply. a comprehensive set of power-saving m ode allows the design of low-power applications. these features make the stm32f410x8/b micr ocontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances ? mobile phone sensor hub figure 2 shows the general block diagram of the devices. docid028094 rev 5 13/142 stm32f410x8/b description 31 table 2. stm32f410x8/b features and peripheral counts peripherals stm32 f410 t8y stm32 f410 tby stm32 f410 c8u stm32 f410 cbu stm32 f410 c8t stm32 f410 cbt stm32 f410 r8t stm32 f410 rbt stm32 f410 r8i stm32 f410 rbi flash memory in kbytes 64 128 64 128 64 128 64 128 64 128 sram in kbytes system 32 timers general- purpose 4 low-power timer 1 advanced- control 1 random number generator 1 communication interfaces spi/ i 2 s1 3 i 2 c2 3 usart 2 3 gpios 23 36 50 12-bit adc number of channels 1 410 16 12-bit dac number of channels 1 1 maximum cpu frequency 100 mhz operating voltage 1.7 to 3.6 v 1.8 to 3.6 v 1.7 to 3.6 v 1.8 to 3.6 v 1.7 to 3.6 v operating temperatures ambient temperatures: ? 40 to +85 c / ? 40 to + 105 c / ? 40 to + 125 c junction temperature: ?40 to + 130 c package wlcsp36 ufqfpn48 lqfp48 lqfp64 ufbga64 description stm32f410x8/b 14/142 docid028094 rev 5 2.1 compatibility with stm32f4 series the stm32f410x8/b are fully software and fe ature compatible with the stm32f4 series (stm32f42x, stm32f401, stm32f43x, stm32f41x, stm32f405 and stm32f407) the stm32f410x8/b can be used as drop-in replacement of the other stm32f4 products but some slight changes have to be done on the pcb board. figure 1. compatible board design for lqfp64 package 1. for stm32f410xb devices, pin 54 is bonded to pb11 instead of pd2. 0 6 y 9 9 & $ 3 l q f u h d v h g w r ? i ( 6 5 ? r u e h o r z 9 6 6 9 6 6 6 7 0 ) [ 6 7 0 ) 6 7 0 ) o l q h 9 ' ' 9 ' ' 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 b 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 & $ 3 b 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 b 9 ' ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 b 9 ' ' 9 6 6 3 % 9 ' ' 9 6 6 9 6 6 9 ' ' 9 & $ 3 l q f u h d v h g w r ? i ( 6 5 ? r u e h o r z 6 7 0 ) [ % 3 % q r w d y d l o d e o h d q \ p r u h 5 h s o d f h g e \ 9 & $ 3 b 3 & 3 & 3 & 3 $ 3 $ 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 % 3 % 9 & $ 3 b 9 ' ' 9 6 6 9 ' ' 9 6 6 9 6 6 9 ' ' 3 ' 3 % 3 % 3 ' 3 % 3 % 3 % 3 % docid028094 rev 5 15/142 stm32f410x8/b description 31 figure 2. stm32f410x8/b block diagram 1. the timers connected to apb2 are clocke d from timxclk up to 100 mhz, while the timers connected to apb1 are clocked from timxclk up to 100 mhz. 0 6 y 9 . % ) o d v k p h p r u \ * 3 , 2 3 2 5 7 $ $ + % $ 3 % ( ; 7 , 7 : . 8 3 $ ) 3 $ > @ 7 , 0 3 : 0 8 6 $ 5 7 5 ; 7 ; 6 & . & 7 6 5 7 6 d v $ ) 6 3 , , 6 d q d o r j l q s x w v 9 ' ' 5 ( ) b $ ' & $ / $ 5 0 b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 9 ' ' $ 9 6 6 $ 1 5 6 7 v p f d u g l u ' $ e 9 % $ 7 w r 9 ' 0 $ 6 & / 6 ' $ 6 0 % $ d v $ ) , & ) 0 6 0 % 8 6 - 7 $ * 6 : $ 5 0 & r u w h [ 0 & r u w h [ 0 0 + ] 1 9 , & ( 7 0 0 3 8 ) 3 8 ' 0 $ 6 w u h d p v ) , ) 2 $ & & ( / & $ & + ( $ + % 0 + ] 8 6 $ 5 7 0 % s v 7 h p s h u d w x u h v h q v r u $ ' & , ) # 9 ' ' $ 3 2 5 3 ' 5 % 2 5 6 x s s o \ v x s h u y l v l r q # 9 ' ' $ 3 9 ' , q w 3 2 5 u h v h w ; 7 $ / n + ] 0 $ 1 $ * 7 5 7 & 5 & + 6 5 & / 6 3 : 5 l q w h u i d f h : ' * . # 9 % $ 7 # 9 ' ' $ : 8 5 h v h w f o r f n f r q w u r o 3 / / $ 3 % & / . 9 r o w d j h u h j x o d w r u w r 9 9 ' ' w r 9 9 6 6 9 & $ 3 b 9 ' ' 3 r z h u p d q d j p w # 9 ' ' 6 7 $ 0 3 % d f n x s u h j l v w h u $ + % e x v p d w u l [ 6 0 $ 3 % 0 + ] / 6 7 , 0 f k d q q h o v d v $ ) 7 , 0 ' % 8 6 $ 3 % 0 + ] p d [ - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 ' 2 6 : ' - 7 ' 2 7 5 $ & ( & / . 7 5 $ & ( ' > @ , % 8 6 6 % 8 6 ' 0 $ 6 w u h d p v ) , ) 2 3 % > @ 3 & > @ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & e 7 , 0 e v p f d u g l u ' $ 8 6 $ 5 7 f k d q q h o d v $ ) 5 ; 7 ; 6 & . d v $ ) , & 6 0 % 8 6 , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) 6 3 , 6 0 2 6 , 0 , 6 2 6 & . 1 6 6 : 6 0 & . d v $ ) 5 ; 7 ; 6 & . & 7 6 5 7 6 d v $ ) 8 6 $ 5 7 v p f d u g l u ' $ e f k d q q h o v d v $ ) ' 0 $ $ + % $ 3 % / 6 2 6 & b , 1 2 6 & b 2 8 7 + & / . ; 7 $ / 2 6 & 0 + ] . % 6 5 $ 0 : : ' * $ 3 % & / . $ + % 3 & / . & 5 & 3 + > @ * 3 , 2 3 2 5 7 + 0 2 6 , 6 ' 0 , 6 2 6 & . 1 6 6 : 6 d v $ ) 6 3 , , 6 0 2 6 , 6 ' 0 , 6 2 6 & . 1 6 6 : 6 d v $ ) 5 1 * 3 : 0 3 : 0 ( 7 5 % . , 1 d v $ ) # 9 ' ' $ 3 & / . / 3 7 , 0 e f k d q q h o v & + 2 , 7 5 d v $ ) 7 , 0 ( 5 e ' $ & # 9 ' ' $ ' $ & d v $ ) , 7 ) functional overview stm32f410x8/b 16/142 docid028094 rev 5 3 functional overview 3.1 arm ? cortex ? -m4 with fpu core with embedded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc proces sor features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal pr ocessing and complex algorithm execution. its single precision fpu (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f410x8/b devices are compatib le with all arm tools and software. figure 2 shows the general block di agram of the stm32f410x8/b. note: cortex ? -m4 with fpu is binary compatible with cortex ? -m3. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 125 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 100 mhz. 3.3 batch acquisition mode (bam) the batch acquisition mode allows enhanced power efficiency during data batching. it enables data acquisition through any communicati on peripherals directly to memory using the dma in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and art). for example in an audio system, a smart combination of pdm audio samp le acquisition and processing from the i2s directly to ram (flash and art ? stopped) with the dma using bam followed by some very short processing from flash allows to dras tically reduce the power consumption of the application. a dedicated application note (an4515) describes how to implement the stm32f410x8/b bam to allow the best power efficiency. docid028094 rev 5 17/142 stm32f410x8/b functional overview 31 3.4 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 3.5 embedded flash memory the devices embed up to 128 kbytes of flas h memory available for storing programs and data, plus 512 bytes of otp memory organized in 16 blocks which can be independently locked. to optimize the power consumption the flash me mory can also be switched off in run or in sleep mode (see section 3.18: low-power modes ). two modes are available: flash in stop mode or in deepsleep mode (trade off between power saving and startup time. before disabling the flash, the code mu st be executed from the internal ram. 3.6 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.7 embedded sram all devices embed 32 kbytes of system sram which can be accessed (read/write) at cpu clock speed with 0 wait states functional overview stm32f410x8/b 18/142 docid028094 rev 5 3.8 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the masters (cpu, dmas) and the slaves (flash memory, ram, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-spe ed peripherals work simultaneously. figure 3. multi-ahb matrix 3.9 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? adc ? dac. 0 6 y 9 $ 5 0 & r u w h [ 0 * 3 ' 0 $ * 3 ' 0 $ % x v p d w u l [ 6 6 6 6 6 6 6 , & 2 ' ( ' & 2 ' ( $ & & ( / ) o d v k . % 6 5 $ 0 . e \ w h v 0 0 0 , e x v ' e x v 6 e x v ' 0 $ b 3 , ' 0 $ b 0 ( 0 ' 0 $ b 0 ( 0 ' 0 $ b 3 0 $ + % s h u l s k $ 3 % $ 3 % docid028094 rev 5 19/142 stm32f410x8/b functional overview 31 3.10 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the cortex ? -m4 with fpu. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 3.11 external interrupt /event controller (exti) the external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 50 gpios can be connected to the 16 external interrupt lines. 3.12 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory- trimmed to offer 1% accuracy at 25 c. the application can then select as system clock eit her the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a so ftware interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 100 mhz. sim ilarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly us ed external oscillator fails). several prescalers allow the configuration of the ahb bus, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maxi mum frequency of the ahb bus and high- speed apb domains is 100 mhz. the maximum allowed freq uency of the low-speed apb domain is 50 mhz. functional overview stm32f410x8/b 20/142 docid028094 rev 5 3.13 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the bootloader is located in system memory. it is used to reprogram the flash memory by using the interfaces described in table 3 . refer to table 9: stm32f410x8/b pin definitions ) for the gpios available on the selected package. for more detailed information on the bootloader, refer to application note: an2606, stm32? microcontroller system memory boot mode . 3.14 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os with the internal supervisor (por/pdr) disabled, provided externally through v dd pins. requires the use of an external power supply supervisor connected to the vdd and pdr_on pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively, with decoupling technique. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. table 3. embedded bootloader interfaces package usart1 usart2 i2c1 i2c2 i2c4 fm+ spi1 spi3 wlcsp36 x pa2/pa3 pb6/pb7 x pb10/pb3 pa15/pa5 /pb4/pb5 x ufqfpn48 pa9/pa10 x pb14/pb15 pa4/pa5/ pa6/pa7 x lqfp64 pb10/pb11 pb12/pb13 /pc2/pc3 docid028094 rev 5 21/142 stm32f410x8/b functional overview 31 3.15 power supply supervisor 3.15.1 internal reset on this feature is available for v dd operating voltage range 1.8 v to 3.6 v. the internal power supply supervisor is enabled by holding pdr_on high. the device has an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process st arts, either to confirm or modify default thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.15.2 internal reset off this feature is available on wlcsp36 package only. the internal power-on reset (por) / power-down reset (pdr) circuitry is dis abled by setting the pdr_on pin to low. an external power supply supervisor should monitor v dd and should set the device in reset mode when v dd is below 1.7 v. nrst should be conn ected to this external power supply supervisor. refer to figure 4: power supply supervisor interconnection with internal reset off . figure 4. power supply supervisor inte rconnection with internal reset off (1) 1. the prd_on pin is avai lable on wlcsp36 package only. 0 6 y 9 3 ' 5 b 2 1 9 ' ' 1 5 6 7 ( [ w h u q d o 9 ' ' s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 ' ' 9 9 ' ' functional overview stm32f410x8/b 22/142 docid028094 rev 5 a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . 3.16 voltage regulator the regulator has three operating modes: ? main regulator mode (mr) ? low power regulator (lpr) ? power-down the three power modes configured by software: ? mr is used in the nominal regulation mode (with different voltage scaling in run) in main regulator mode (mr mode), different voltage scaling are provided to reach the best compromise between maximum fr equency and dynamic power consumption. ? lpr is used in the stop modes the lp regulator mode is configured by software when entering stop mode. ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. an external ceramic capacitor should be connected to the v cap_1 pin. 3.16.1 internal power suppl y supervisor availability table 4. regulator on/off and internal power supply supervisor availability package power supply supervisor on power supply supervisor off ufqfpn48 yes no wlcsp36 yes pdr_on set to vdd yes pdr_on set to v ss (1) 1. an external power supervisor must be used (refer to section 3.15.2: internal reset off ). lqfp64 yes no docid028094 rev 5 23/142 stm32f410x8/b functional overview 31 3.17 real-time clock (rtc ) and backup registers the backup domain includes: ? the real-time clock (rtc) ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc features a reference clock detection, a more precise second source clock (50 or 60 hz) can be us ed to enhance the calendar precision. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.18: low-power modes ). additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 3.18 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. to further reduce the power consumption, the flash memory can be switched off before entering in sleep mode. note that this requires a code execution from the ram. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc functional overview stm32f410x8/b 24/142 docid028094 rev 5 and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the rtc and the low-power timer (lptim1) can remain active in stop mode. they can consequently be used to wake up the device from this mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external li nes, the pvd output, lptim1, the rtc alarm/ wakeup/ tamper/ time stamp events). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm/ wakeup/ tamper/time stamp event occurs. standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. 3.19 v bat operation the vbat pin allows to power the device v bat domain from an external battery, an external super-capacitor, or from v dd when no external battery and an external super-capacitor are present. v bat operation is activated when v dd is not present. the vbat pin supplies the rtc and the backup registers. note: when the microcontroller is supplied from vba t, external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and vbat pin should be connected to v dd . 3.20 timers and watchdogs the devices embed one advanced-control time r, four general purpose timers, one low power timer, two watchdog timers and one systick timer. all timer counters can be frozen in debug mode. table 5 compares the features of the advanced-control and general-purpose timers. docid028094 rev 5 25/142 stm32f410x8/b functional overview 31 table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complemen- tary output max. interface clock (mhz) max. timer clock (mhz) advanced -control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 100 100 general purpose tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 50 100 tim9 16-bit up any integer between 1 and 65536 no 2 no 100 100 tim11 16-bit up any integer between 1 and 65536 no 1 no 100 100 basic tim6 16-bit up any integer between 1 and 65536 yes 0 no 50 100 low- power lptim1 16-bit up between 1 and 128 no 2 no 50 100 functional overview stm32f410x8/b 26/142 docid028094 rev 5 3.20.1 advanced-control timers (tim1) the advanced-control timer (tim1) can be seen as three-phase pwm generator multiplexed on 4 independent channels. it has complementary pwm outputs with programmable inserted dead times. it can also be considered as a complete general-purpose timer. its 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, it has the same features as the general-purpose timx timers. if configured as a 16-bit pwm g enerator, it has full mo dulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 supports independent dma request generation. 3.20.2 general-purpose timers (tim5, tim9 and tim11) there are three synchronizable general-purpo se timers embedded in the stm32f410x8/b (see table 5 for differences). ? tim5 the stm32f410x8/b devices includes a full-featured general-purpose timer, tim5. tim5 timer is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. it features four independent channels for i nput capture/output compare, pwm or one- pulse mode output. tim5 can operate in conjunction with the other general-purpose timers and tim1 advanced-control timer via the timer link feature for synchronization or event chaining. tim5 general-purpose timer can be used to generate pwm output. all tim5 channels have independent dma request generation. they are capable of handling quadrature (incremental) encoder sign als and the digital outputs from 1 to 4 hall-effect sensors. ? tim9 and tim11 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim11 features one independent channe l, whereas tim9 has two independent channels for input capture/ou tput compare, pwm or one-pulse mode output. they can be synchronized with tim5 full-featured gener al-purpose timer or used as simple time bases. 3.20.3 basic timer (tim6) this timer is mainly used for dac triggering and waveform generation. it can also operate as generic 16-bit timers. tim6 supports independent dma request generation. docid028094 rev 5 27/142 stm32f410x8/b functional overview 31 3.20.4 low-power timer (lptim1) the devices embed one low-power timer. this timer features an independent clock and runs in stop mode if it is clocked by lse, lsi or by an external clock. it is able to wake up the system from stop mode. the low-power timer main features are the following: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous/ one shot mode ? selectable software/ hardware input trigger ? selectable clock source ? internal clock sources: lse, lsi, hsi or apb1 clock ? external clock source over lptim input (working even when no internal clock source is running and used by pulse-counter applications). ? programmable digital glitch filter ? encoder mode ? active in stop mode. 3.20.5 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 3.20.6 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.20.7 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. functional overview stm32f410x8/b 28/142 docid028094 rev 5 3.21 inter-integrated circuit interface (i 2 c) the devices feature up to three i 2 c bus interfaces which can operate in multimaster and slave modes: ? one i 2 c interface supports the standard mode (up to 100 khz), fast-mode (up to 400 khz) modes and fast-mode plus (up to 1 mhz). ? two i 2 c interfaces support the standard mode (up to 100 khz) and the fast mode (up to 400 khz). their frequency can be increased up to 1 mhz. for more details on the complete solution, refer to the nearest stmicroelectronics sales office. all i 2 c interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave) and embed a hardware crc generation/verification. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 6 ). 3.22 universal synchronous/asynch ronous receiver transmitters (usart) the devices embed three universal synchron ous/asynchronous receiver transmitters (usart1, usart2 and usart6). these three interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 12.5 mbit/s. the usart2 interface communicates at up to 6.25 bit/s. usart1 and usart2 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like commu nication capability. all interfaces can be served by the dma controller. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks docid028094 rev 5 29/142 stm32f410x8/b functional overview 31 3.23 serial peripheral interface (spi) the devices feature three spis in slave and master modes in full-duplex and simplex communication modes. spi1 and spi5 can communicate at up to 50 mbit/s, spi2 can communicate at up to 25 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurab le to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. 3.24 inter-integr ated sound (i 2 s) three standard i 2 s interfaces (multiplexed with spi1 to spi5) are available. they can be operated in master or slave mode, in simp lex communication modes and can be configured to operate with a 16-/32-bit resolution as an input or output channel. all the i2sx audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i 2 sx can be served by the dma controller. 3.25 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. table 7. usart feature comparison usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x (1) x x x x 6.25 12.5 apb2 (max. 100 mhz) usart2 x x (1) xx (1) xx (1) 3.12 6.25 apb1 (max. 50 mhz) usart6 (1) xn.axx (1)(2) xx (1)(2) 6.25 12.5 apb2 (max. 50 mhz) 1. not available on wlcsp36 package. 2. not available on ufqfpn48 package. functional overview stm32f410x8/b 30/142 docid028094 rev 5 3.26 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allo wing maximum i/o toggling up to 100 mhz. 3.27 analog-to-digita l converter (adc) one 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-sho t or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, the adcs could be triggered by any of tim1 or tim5 timer. 3.28 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the adc_in18 input channel wh ich is used to convert the sensor output voltage into a digital value. refer to the reference manual for additional information. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.29 digital-to-analog converter (dac) one 12-bit buffered dac channel can be used to convert a digital signal into an analog voltage signal output. the chosen design stru cture is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supp orts the following features: ? 8-bit or 12-bit monotonic output ? buffer offset calibration (factory and user trimming) ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation docid028094 rev 5 31/142 stm32f410x8/b functional overview 31 ? triangular-wave generation ? dma capability for each channel ? external triggers for conversion ? sample and hold low-power mode, with internal or external capacitor the dac channel is triggered through tim6 update output that is also connected to different dma channels. 3.30 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.31 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f410x8/b through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using any high-speed channel available. real-time instruction and da ta flow activity can be recorded and then formatted for display on the host computer th at runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. pinouts and pin description stm32f410x8/b 32/142 docid028094 rev 5 4 pinouts and pin description figure 5. lqfp48 pinout 1. the above figure shows the package top view. figure 6. lqfp64 pinout 1. the above figure shows the package top view. 0 6 y 9 / 4 ) 3 9 % $ 7 3 & $ 1 7 , b 7 $ 0 3 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ : . 8 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 9 ' ' 3 $ 3 $ 3 % 3 % 3 % 9 & $ 3 b 9 6 6 9 ' ' 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 ' ' 3 ' 5 b 2 1 % 2 2 7 3 % 3 $ 9 6 6 3 % 3 % 3 % 3 % 3 % 3 $ 0 v y 9 / 4 ) 3 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 3 & 3 $ 9 6 6 3 $ 3 & 3 % 9 ' ' 3 $ 3 & 9 & $ 3 b 3 $ 3 $ 9 6 6 3 % 3 % 3 % 9 ' ' 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 6 6 % 2 2 7 3 % 3 & 3 % 3 % 3 % 3 & 3 % 3 % 3 $ 3 % 3 % 3 & 3 $ docid028094 rev 5 33/142 stm32f410x8/b pinouts and pin description 43 figure 7. ufqfpn48 pinout 1. the above figure shows the package top view. figure 8. ufbga64 pinout 1. the above figure shows the package top view. 0 6 9 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 9 6 6 3 $ 8 ) 4 ) 3 1 3 $ 9 6 6 $ 9 5 ( ) 3 $ 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 9 6 6 3 % 9 & $ 3 b 3 % 3 % 3 % 3 % 9 % $ 7 3 & 3 & 2 6 & b , 1 3 + 2 6 & b , 1 1 5 6 7 3 % 3 % 9 ' ' 3 & 2 6 & b 2 8 7 3 + 2 6 & b 2 8 7 0 6 y 9 3 & 2 6 & b , 1 9 % $ 7 3 % % 2 2 7 3 % 3 & 3 $ 3 $ $ % & ' ( ) * + 3 & 2 6 & b 2 8 7 3 & $ 1 7 , b 7 $ 0 3 3 % 3 % 3 % 3 & 3 $ 3 $ 3 + 2 6 & b , 1 9 6 6 3 ' 5 b 2 1 3 % 3 % 3 $ 3 + 2 6 & b 2 8 7 9 ' ' 3 & 1 5 6 7 3 & 3 & 9 6 6 $ 3 & 9 5 ( ) 3 $ : . 8 3 9 ' ' $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 9 ' ' 3 & 3 $ 3 $ 3 $ 9 ' ' 3 % 9 & $ 3 b 3 % 3 % 3 & 3 $ 3 % 3 % 3 & 3 $ 9 6 6 3 & 3 $ 3 % 3 % 3 % 3 & 3 & pinouts and pin description stm32f410x8/b 34/142 docid028094 rev 5 figure 9. wlcsp36 pinout 1. the above figure shows the package bump side. 0 6 y 9 $ % ( ' & ) 9 ' ' 3 & 2 6 & b , 1 3 + 2 6 & b , 1 1 5 6 7 9 ' ' $ 9 5 ( ) 9 6 6 9 % $ 7 3 & 2 6 & b 2 8 7 3 $ 3 $ 3 % 3 ' 5 b 2 1 3 + 2 6 & b 2 8 7 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 $ 3 % 3 $ 9 ' ' 3 $ 9 & $ 3 b 9 6 6 3 & % 2 2 7 3 $ 3 $ 3 % 3 % 3 % 9 6 6 $ 9 5 ( ) table 8. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input/ output pin i/o structure ft 5 v tolerant i/o tc standard 3.3 v i/o b dedicated boot0 pin nrst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers docid028094 rev 5 35/142 stm32f410x8/b pinouts and pin description 43 table 9. stm32f410x8/b pin definitions pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions wlcsp36 lqfp48 ufqfpn48 lqfp64 ufbga64 b5 1 1 1 a2 vbat s - - - vbat - - - - c2 vss s - - - - c4 2 2 2 b2 pc13 i/o ft (2)(3) eventout rtc_tamp1, rtc_out, rtc_ts b6 3 3 3 a1 pc14- osc32_in i/o ft (2)(3) (4) eventout osc32_in c6 4 4 4 b1 pc15- osc32_out i/o ft (2)(4) eventout osc32_out -- - -d2 vdd s-- - - c5 5 5 5 c1 ph0 - osc_in i/o ft (4) eventout osc_in d6 6 6 6 d1 ph1 - osc_out i/o ft (4) eventout osc_out d5 7 7 7 e1 nrst nr st -- - - -- - 8d3 pc0 i/oft- lptim1_in1, eventout adc1_10, wkup2 - - - 9 e2 pc1 i/o ft - lptim1_out, eventout adc1_11, wkup3 -- -10e3 pc2 i/oft- lptim1_in2, spi2_miso, eventout adc1_12 -- -11f2 pc3 i/oft- lptim1_etr, spi2_mosi/i2s2_sd, eventout adc1_13 e6 8 8 12 f1 vssa/vref- s - - - - f6 9 9 13 - vdda/vref+ s - - - - - - - - g1 vref+ s - - - - - - - - h1 vdda s - - - - e5 10 10 14 g2 pa0 i/o ft - tim5_ch1, usart2_cts, eventout adc1_0, wkup1 -111115h2 pa1 i/oft- tim5_ch2, usart2_rts, eventout adc1_1 pinouts and pin description stm32f410x8/b 36/142 docid028094 rev 5 e4 12 12 16 f3 pa2 i/o ft - tim5_ch3, tim9_ch1, i2s2_ckin, usart2_tx, eventout adc1_2 f5 13 13 17 g3 pa3 i/o ft - tim5_ch4, tim9_ch2, i2s2_mck, usart2_rx, eventout adc1_3 - - - 18 d5 vss s - - - - -- -19e4 vdd s-- - - -141420h3 pa4 i/oft- spi1_nss/i2s1_ws, usart2_ck, eventout adc1_4 f4 15 15 21 f4 pa5 i/o tc - spi1_sck/i2s1_ck, eventout adc1_5, dac_out1 -161622g4 pa6 i/oft- tim1_bkin, spi1_miso, i2s2_mck, eventout adc1_6 -171723h4 pa7 i/oft- tim1_ch1n, spi1_mosi/i2s1_sd, eventout adc1_7 -- -24g5 pc4 i/oft- tim9_ch1, eventout adc1_14 -- -25h5 pc5 i/oft- tim9_ch2, i2c4_smba, eventout adc1_15 - 18 18 26 f5 pb0 i/o ft - tim1_ch2n, spi5_sck/i2s5_ck, eventout adc1_8 - 19 19 27 g6 pb1 i/o tc - tim1_ch3n, spi5_nss/i2s5_ws, eventout adc1_9 f3 20 20 28 h6 pb2 i/o ft - lptim1_out, eventout boot1 table 9. stm32f410x8/b pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions wlcsp36 lqfp48 ufqfpn48 lqfp64 ufbga64 docid028094 rev 5 37/142 stm32f410x8/b pinouts and pin description 43 e3 21 21 29 g7 pb10 i/o ft - i2c2_scl, spi2_sck/i2s2_ck, i2s1_mck, i2c4_scl, eventout - e2 22 22 30 h7 vcap_1 s - - - - f2 23 23 31 d6 vss s - - - - f1 24 24 32 e5 vdd s - - - - e1 25 25 33 h8 pb12 i/o ft - tim1_bkin, tim5_ch1, i2c2_smba, spi2_nss/i2s2_ws, eventout - - 26 26 34 g8 pb13 i/o ft - tim1_ch1n, i2c4_smba, spi2_sck/i2s2_ck, eventout - - 27 27 35 f8 pb14 i/o ft - tim1_ch2n, i2c4_sda, spi2_miso, eventout - - 28 28 36 f7 pb15 i/o ft - rtc_50hz, tim1_ch3n, i2c4_scl, spi2_mosi/i2s2_sd, eventout - -- -37f6 pc6 i/oft- traceclk, i2c4_scl, i2s2_mck, usart6_tx, eventout - -- -38e7 pc7 i/oft- i2c4_sda, spi2_sck/i2s2_ck, i2s1_mck, usart6_rx, eventout - -- -39e8 pc8 i/oft- usart6_ck, eventout - -- -40d8 pc9 i/oft- mco_2, i2c4_sda, i2s2_ckin, eventout - table 9. stm32f410x8/b pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions wlcsp36 lqfp48 ufqfpn48 lqfp64 ufbga64 pinouts and pin description stm32f410x8/b 38/142 docid028094 rev 5 d1 29 29 41 c8 pa8 i/o ft - mco_1, tim1_ch1, i2c4_scl, usart1_ck, eventout - -303042 b8 pa9 i/oft- tim1_ch2, usart1_tx, eventout - -313143 e6 pa10 i/oft- tim1_ch3, spi5_mosi/i2s5_sd, usart1_rx, eventout - -323244d7 pa11 i/oft- tim1_ch4, usart1_cts, usart6_tx, eventout - d2 33 33 45 a8 pa12 i/o ft - tim1_etr, spi5_miso, usart1_rts, usart6_rx, eventout - c1 34 34 46 c7 pa13 i/o ft - jtms-swdio, eventout - b1 35 35 47 d5 vss s - - - - -363648 - vdd s- - - - a1 - - - - vdd s - - - - b2 37 37 49 b7 pa14 i/o ft - jtck-swclk, eventout - a2 38 38 50 a7 pa15 i/o ft - jtdi, spi1_nss/i2s1_ws, usart1_tx, eventout - -- -51c6 pc10 i/oft- traced0, tim5_ch2, eventout - -- -52b6 pc11 i/oft- traced1, tim5_ch3, eventout - -- -53a6 pc12 i/oft- traced2, tim11_ch1, eventout - table 9. stm32f410x8/b pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions wlcsp36 lqfp48 ufqfpn48 lqfp64 ufbga64 docid028094 rev 5 39/142 stm32f410x8/b pinouts and pin description 43 - - - 54 b5 pb11 i/o ft - traced3, tim5_ch4, i2c2_sda, i2s2_ckin, eventout - c2 39 39 55 a5 pb3 i/o ft - jtdo-swo, i2c4_sda, spi1_sck/i2s1_ck, usart1_rx, i2c2_sda, eventout - d3 40 40 56 c5 pb4 i/o ft - jtrst, spi1_miso, eventout - a3 41 41 57 d4 pb5 i/o ft - lptim1_in1, i2c1_smba, spi1_mosi/i2s1_sd, eventout - b3 42 42 58 c4 pb6 i/o ft - lptim1_etr, i2c1_scl, usart1_tx, eventout - c3 43 43 59 b4 pb7 i/o ft - lptim1_in2, i2c1_sda, usart1_rx, eventout - d4 44 44 60 a4 boot0 i b - - boot0 a4 45 45 61 b3 pb8 i/o ft - lptim1_out, i2c1_scl, spi5_mosi/i2s5_sd, eventout - - - 46 62 a3 pb9 i/o ft - tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, i2c2_sda, eventout - a5 46 47 63 - vss s - - - - b4 47 - - c3 pdr_on i ft - - - a6 48 48 64 - vdd s - - - - 1. function availability depends on the chosen device. table 9. stm32f410x8/b pin definitions (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions wlcsp36 lqfp48 ufqfpn48 lqfp64 ufbga64 pinouts and pin description stm32f410x8/b 40/142 docid028094 rev 5 2. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a curr ent source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the stm32f410x8/breference manual. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). stm32f410x8/b pinouts and pin description docid028094 rev 5 41/142 table 10. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim1/lptim1 tim5 tim9/ tim11 i2c1/i2c2 /i2c4 spi1/i2s1/s pi2/i2s2 spi1/i2s1/ spi2/i2s2/ spi5/i2s5 usart1/ usart2 usart6 i2c2/ i2c4 -----sys_af port a pa0 - - tim5_ ch1 -- - - usart2_ cts - - - - - - - eventout pa1 - - tim5_ ch2 -- - - usart2_ rts - - - - - - - eventout pa2 - - tim5_ ch3 tim9_ ch1 - i2s2_ ckin - usart2_ tx - - - - - - - eventout pa3 - - tim5_ ch4 tim9_ ch2 - i2s2_mck - usart2_ rx - - - - - - - eventout pa4 - - - - - spi1_nss/ i2s1_ws - usart2_ ck - - - - - - - eventout pa5 - - - - - spi1_sck/ i2s1_ck - - - - - - - - - eventout pa6 - tim1_bkin - - - spi1_miso i2s2_mck - - - - - - - - eventout pa7 - tim1_ch1n - - - spi1_mosi /i2s1_sd - - - - - - - - - eventout pa8 mco_1 tim1_ch1 - - i2c4_ scl -- usart1_ ck - - - - - - - eventout pa9 - tim1_ch2 - - - - - usart1_ tx - - - - - - - eventout pa10 - tim1_ch3 - - - - spi5_mosi /i2s5_sd usart1_ rx - - - - - - - eventout pa11 - tim1_ch4 - - - - - usart1_ cts usart6 _tx - - - - - - eventout pa12 - tim1_etr - - - - spi5_miso usart1_ rts usart6 _rx - - - - - - eventout pa13 jtms- swdio - - - - - - - - - - - - - - eventout pa14 jtck- swclk - - - - - - - - - - - - - - eventout pa15 jtdi - - - - spi1_nss/ i2s1_ws - usart1_ tx - - - - - - - eventout pinouts and pin description stm32f410x8/b 42/142 docid028094 rev 5 port b pb0 - tim1_ch2n - - - - spi5_sck/ i2s5_ck - - - - - - - - eventout pb1 - tim1_ch3n - - - - spi5_nss/ i2s5_ws - - - - - - - - eventout pb2 - lptim1_out - - - - - - - - - - - - - eventout pb3 jtdo- swo --- i2c4_ sda spi1_sck/i 2s1_ck - usart1_ rx - i2c2_ sda - - - - - eventout pb4 jtrst - - - - spi1_miso - - - - - - - - - eventout pb5 - lptim1_in1 - - i2c1_ smba spi1_mosi /i2s1_sd - - - - - - - - - eventout pb6 - lptim1_etr - - i2c1_ scl -- usart1_ tx - - - - - - - eventout pb7 - lptim1_in2 - - i2c1_ sda -- usart1_ rx - - - - - - - eventout pb8 - lptim1_out - - i2c1_ scl - spi5_mosi /i2s5_sd - - - - - - - - eventout pb9 - - - tim11_ ch1 i2c1_ sda spi2_nss/ i2s2_ws --- i2c2_ sda - - - - - eventout pb10 - - - - i2c2_ scl spi2_sck/ i2s2_ck i2s1_mck - - i2c4_ scl - - - - - eventout pb11 traced3 - tim5_ ch4 - i2c2_ sda i2s2_ckin - - - - - - - - - eventout pb12 - tim1_bkin tim5_ ch1 - i2c2_ smba spi2_nss/ i2s2_ws - - - - - - - - - eventout pb13 - tim1_ch1n - - i2c4_ smba spi2_sck /i2s2_ck - - - - - - - - - eventout pb14 - tim1_ch2n - - i2c4_ sda spi2_miso - - - - - - - - - eventout pb15 rtc_ 50hz tim1_ch3n - - i2c4_ scl spi2_mosi /i2s2_sd - - - - - - - - - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim1/lptim1 tim5 tim9/ tim11 i2c1/i2c2 /i2c4 spi1/i2s1/s pi2/i2s2 spi1/i2s1/ spi2/i2s2/ spi5/i2s5 usart1/ usart2 usart6 i2c2/ i2c4 -----sys_af stm32f410x8/b pinouts and pin description docid028094 rev 5 43/142 port c pc0 - lptim1_in1 - - - - - - - - - - - - - eventout pc1 - lptim1_out - - - - - - - - - - - - - eventout pc2 - lptim1_in2 - - - spi2_miso - - - - - - - - - eventout pc3 - lptim1_etr - - - spi2_mosi /i2s2_sd - - - - - - - - - eventout pc4 - - - tim9_ ch1 - - - - - - - - - - - eventout pc5 - - - tim9_ ch2 i2c4_ smba - - - - - - - - - - eventout pc6 trace clk --- i2c4_ scl i2s2_mck - - usart6 _tx - - - - - - eventout pc7 - - - - i2c4_ sda spi2_sck/ i2s2_ck i2s1_mck - usart6 _rx - - - - - - eventout pc8 - - - - - - - - usart6 _ck - - - - - - eventout pc9 mco_2 - - - i2c4_ sda i2s2_ckin - - - - - - - - - eventout pc10 traced0 - tim5_ ch2 - - - - - - - - - - - - eventout pc11 traced1 - tim5_ ch3 - - - - - - - - - - - - eventout pc12 traced2 - - tim11_ ch1 - - - - - - - - - - - eventout pc13 - - - - - - - - - - - - - - - eventout pc14 - - - - - - - - - - - - - - - eventout pc15 - - - - - - - - - - - - - - - eventout port h ph0 - - - - - - - - - - - - - - - eventout ph1 - - - - - - - - - - - - - - - eventout table 10. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys_af tim1/lptim1 tim5 tim9/ tim11 i2c1/i2c2 /i2c4 spi1/i2s1/s pi2/i2s2 spi1/i2s1/ spi2/i2s2/ spi5/i2s5 usart1/ usart2 usart6 i2c2/ i2c4 -----sys_af memory mapping stm32f410x8/b 44/142 docid028094 rev 5 5 memory mapping the memory map is shown in figure 10 . figure 10. memory map 0 6 y 9 0 e \ w h e o r f n & r u w h [ 0 v l q w h u q d o s h u l s k h u d o v 0 e \ w h e o r f n 1 r w x v h g 0 e \ w h e o r f n 3 h u l s k h u d o v 0 e \ w h e o r f n 6 5 $ 0 [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ & [ ' ) ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 0 e \ w h e o r f n & r g h [ [ ) ) ) ) ) ) ) [ 5 h v h u y h g [ ) ) [ [ ) ) ) ) [ [ ' ) ) ) ) ) ) ) 5 h v h u y h g 6 5 $ 0 . % d o l d v h g e \ e l w e d q g l q j [ [ ) ) ) $ 3 % $ 3 % [ ) ) [ [ ) ) ) ) 5 h v h u y h g [ [ ) ) $ + % ) o d v k p h p r u \ [ [ ) ) ( ) ) ) ) [ ) ) ) & [ ) ) ) & [ [ ) ) ) ) [ [ ) ) ) ) ) ) [ [ ) ) ) ) 5 h v h u y h g 5 h v h u y h g $ o l d v h g w r ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q w k h % 2 2 7 s l q v 6 \ v w h p p h p r u \ [ ) ) ) & [ ) ) ) ) ) ) ) [ ) ) ) $ [ ) ) ) % ) ) ) [ ) ) ) [ ) ) ) ) ) 2 s w l r q e \ w h v [ & r u w h [ 0 l q w h u q d o s h u l s k h u d o v [ ( [ ( ) ) ) ) ) 5 h v h u y h g [ ( [ ) ) ) ) ) ) ) ) 5 h v h u y h g [ % ) ) ) ) ) ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 2 7 3 d u h d o r f n [ ) ) ) [ ) ) ) $ ) docid028094 rev 5 45/142 stm32f410x8/b memory mapping 47 table 11. stm32f410x8/b register boundary addresses (1) bus boundary address peripheral - 0xe010 0000 - 0xffff ffff reserved cortex ? -m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals - 0x5000 0000 - 0xdfff ffff reserved ahb1 0x4008 0400 - 0x4fff ffff reserved 0x4008 0000 - 0x4008 03ff rng 0x4002 6800 - 0x4007 ffff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 4fff reserved 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2800 - 0x4002 2fff reserved 0x4002 2400 - 0x4002 27ff lptim1 0x4002 2000 - 0x4002 23ff reserved 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 0c00 - 0x4002 1bff reserved 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa memory mapping stm32f410x8/b 46/142 docid028094 rev 5 apb2 0x4001 5400- 0x4001 ffff reserved 0x4001 5000 - 0x4001 53ff spi5/i2s5 0x4001 4c00- 0x4001 4fff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff reserved 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff reserved 0x4001 3000 - 0x4001 33ff spi1/i2s1 0x4001 2400 - 0x4001 2ff reserved 0x4001 2000 - 0x4001 23ff adc1 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0400 - 0x4001 0fff reserved 0x4001 0000 - 0x4001 03ff tim1 table 11. stm32f410x8/b register boundary addresses (1) bus boundary address peripheral docid028094 rev 5 47/142 stm32f410x8/b memory mapping 47 apb1 0x4000 7800 - 0x4000 ffff reserved 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6400 - 0x4000 6fff reserved 0x4000 6000 - 0x4000 63ff i2c4 fm+ 0x4000 5c00 - 0x4000 5fff reserved 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 4800 - 0x4000 53ff reserved 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff reserved 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff reserved 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2b ff rtc & bkp registers 0x4000 1400 - 0x4000 27ff reserved 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0000 - 0x4000 0bff reserved 1. the gray color is used for reserved boundary address. table 11. stm32f410x8/b register boundary addresses (1) bus boundary address peripheral electrical characteristics stm32f410x8/b 48/142 docid028094 rev 5 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 11 . figure 11. pin loading conditions - 3 6 # p & - # 5 p i n docid028094 rev 5 49/142 stm32f410x8/b electrical characteristics 118 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 12 . figure 12. input voltage measurement - 3 6 - # 5 p i n 6 ) . electrical characteristics stm32f410x8/b 50/142 docid028094 rev 5 6.1.6 power supply scheme figure 13. power supply scheme 1. to connect pdr_on pin, refer to section 3.15: power supply supervisor . caution: each power supply pair (for example v dd /v ss , v dda /v ssa ) must be decoupled with filtering ceramic capacitors as shown above. these capa citors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filt ering capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 0 6 y 9 l? ]?]??? ~ k ^ ?? <u z d u tl ? o}p] l? ? p]?? ?? u < ?v o o}p] ~ w hu ]p]?o ? z d vo}pw z ? u w > > uxx w} ? ?]?z s d ' w / k? k h d / e e ? v & = ? ex r & s d a x? ?} ?x s s}o?p ? po?}? s > o ?z](? ? / k >}p] s v & = r & &o?z u u}?? s wz ? ex r & w zz k e z ? ? }v??}oo ? s l? lxxx e s ^ ^ l? lxxx e s s ^ ^ s z & v & = r & docid028094 rev 5 51/142 stm32f410x8/b electrical characteristics 118 6.1.7 current consumption measurement figure 14. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 12: voltage characteristics , table 13: current characteristics , and table 14: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. d l 9 % $ 7 9 ' ' 9 ' ' $ , ' ' b 9 % $ 7 , ' ' table 12. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd and v bat ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on ft and tc pins (2) 2. v in maximum value must always be respected. refer to table 13 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4.0 input voltage on any other pin v ss ?0.3 4.0 input voltage for boot0 v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins including v ref- -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.14: absolute maximum ratings (electrical sensitivity) v electrical characteristics stm32f410x8/b 52/142 docid028094 rev 5 table 13. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd_x power lines (source) (1) 160 ma i vss total current out of sum of all v ss_x ground lines (sink) (1) -160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) -100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin -25 i io total output current sunk by sum of all i/o and control pins (2) 120 total output current sourced by sum of all i/os and control pins (2) -120 i inj(pin) (3) injected current on ft and tc pins (4) ?5/+0 injected current on nrst and b pins (4) i inj(pin) total injected current (sum of all i/o and control pins) (5) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to t he external power supply, in the permitted range. 2. this current consumption must be correctl y distributed over all i/os and control pins. 3. negative injection disturbs the analog performance of the device. see note in section 6.3.20: 12-bit adc characteristics . 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 14. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 130 t lead maximum lead temperature during soldering (wlcsp36, lqfp48, lqfp64, ufqfpn48, ufbga64) see note (1) 1. compliant with jedec std j-std-020d (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (roh s directive 2011/65/eu, july 2011). docid028094 rev 5 53/142 stm32f410x8/b electrical characteristics 118 6.3 operating conditions 6.3.1 general operating conditions table 15. general operating conditions symbol parameter conditions min typ max unit f hclk internal ahb clock frequency power scale3: regulator on, vos[1:0] bits in pwr_cr register = 0x01 0-64 mhz power scale2: regulator on, vos[1:0] bits in pwr_cr register = 0x10 0 - 84 power scale1: regulator on, vos[1:0] bits in pwr_cr register = 0x11 0-100 f pclk1 internal apb1 clock frequency - 0 - 50 mhz f pclk2 internal apb2 clock frequency - 0 - 100 mhz v dd standard operating voltage - 1.7 (1) -3.6v v dda (2)(3) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (4) 1.7 (1) -2.4 v analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v bat backup operating voltage - 1.65 - 3.6 v v 12 regulator on: 1.2 v internal voltage on vcap_1 pins vos[1:0] bits in pwr_cr register = 0x01 max frequency 64 mhz 1.08 (5) 1.14 1.20 (5) v vos[1:0] bits in pwr_cr register = 0x10 max frequency 84 mhz 1.20 (5) 1.26 1.32 (5) vos[1:0] bits in pwr_cr register = 0x11 max frequency 100 mhz 1.26 1.32 1.38 v 12 regulator off: 1.2 v external voltage must be supplied on vcap_1 pins max frequency 64 mhz 1.10 1.14 1.20 v max frequency 84 mhz 1.20 1.26 1.32 max frequency 100 mhz 1.26 1.32 1.38 v in input voltage on rst, ft and tc pins (6) 2 v v dd 3.6 v ?0.3 - 5.5 v v dd 2 v ?0.3 - 5.2 input voltage on boot0 pin - 0 - 9 electrical characteristics stm32f410x8/b 54/142 docid028094 rev 5 p d maximum allowed package power dissipation at t a = 85 c (range 6) or 105 c (range 7) (7) lqfp48 - - 364 mw lqfp64 - - 435 ufqfpn48 - - 606 wlcsp36 - - 328 ufbga64 - - 253 power dissipation at t a = 125 c for range 3 (7) lqfp48 - - 91 lqfp64 - - 108 ufqfpn48 - - 151 wlcsp36 - - 81 ufbga64 - - 63 t a ambient temperature for range 6 maximum power dissipation ?40 - 85 c low power dissipation (8) ?40 - 105 ambient temperature for range 7 maximum power dissipation ?40 - 105 low power dissipation (8) ?40 - 125 ambient temperature for range 3 maximum power dissipation -40 - 110 low power dissipation (8) -40 - 130 t j junction temperature range range 6 ?40 - 105 range 7 ?40 - 125 range 3 ?40 - 130 1. v dd /v dda minimum value of 1.7 v with the use of an external power supply supervisor (refer to section 3.15.2: internal reset off ). 2. when the adc is used, refer to table 66: adc characteristics . 3. if vref+ pin is present, it must respect the following condition: vdda-vref+ < 1.2 v. 4. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 5. guaranteed by test in production. 6. to sustain a voltage higher than vdd+0.3, the inter nal pull-up and pull-down resistors must be disabled 7. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 8. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 15. general operating conditions (continued) symbol parameter conditions min typ max unit docid028094 rev 5 55/142 stm32f410x8/b electrical characteristics 118 table 16. features depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) i/o operation clock output frequency on i/o pins (3) possible flash memory operations v dd =1.7 to 2.1 v (4) conversion time up to 1.2 msps 16 mhz (5) 100 mhz with 6 wait states ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 18 mhz 100 mhz with 5 wait states ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 100 mhz with 4 wait states ?i/o compensation works up to 50 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v conversion time up to 2.4 msps 30 mhz 100 mhz with 3 wait states ?i/o compensation works ?up to 100 mhz when v dd = 3.0 to 3.6 v ?up to 50 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. refer to table 57: i/o ac characteristics for frequencies vs. external load. 4. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 3.15.2: internal reset off ). 5. prefetch is not available. refe r to an3430 application note for details on how to adjust performance and power. electrical characteristics stm32f410x8/b 56/142 docid028094 rev 5 6.3.2 vcap_1 external capacitor stabilization for the main regulator is achiev ed by connecting the external capacitor c ext to the vcap_1 pin. c ext is specified in table 17 . figure 15. external capacitor c ext 1. legend: esr is the equivalent series resistance. 6.3.3 operating conditions at pow er-up/power-down (regulator on) subject to general operating conditions for t a . 6.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . table 17. vcap_1 operating conditions symbol paramete r conditions cext capacitance of external capacitor 4.7 f esr esr of external capacitor < 1 0 6 9 ( 6 5 5 / h d n & table 18. operating conditions at power-up / power-down (regulator on) symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 19. operating conditions at pow er-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 rise time rate power-up 20 v cap_1 fall time rate power-down 20 docid028094 rev 5 57/142 stm32f410x8/b electrical characteristics 118 6.3.5 embedded reset and power control block characteristics the parameters given in table 20 are derived from tests performed under ambient temperature and v dd supply voltage @ 3.3v. table 20. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 pls[2:0]=001 (rising edge) 2.23 2.30 2.37 pls[2:0]=001 (falling edge) 2.13 2.19 2.25 pls[2:0]=010 (rising edge) 2.39 2.45 2.51 pls[2:0]=010 (falling edge) 2.29 2.35 2.39 pls[2:0]=011 (rising edge) 2.54 2.60 2.65 pls[2:0]=011 (falling edge) 2.44 2.51 2.56 pls[2:0]=100 (rising edge) 2.70 2.76 2.82 pls[2:0]=100 (falling edge) 2.59 2.66 2.71 pls[2:0]=101 (rising edge) 2.86 2.93 2.99 pls[2:0]=101 (falling edge) 2.65 2.84 3.02 pls[2:0]=110 (rising edge) 2.96 3.03 3.10 pls[2:0]=110 (falling edge) 2.85 2.93 2.99 pls[2:0]=111 (rising edge) 3.07 3.14 3.21 pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v pvdhyst (2) pvd hysteresis - - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 (1) 1.68 1.76 v rising edge 1.64 1.72 1.80 v pdrhyst (2) pdr hysteresis - - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 rising edge 2.53 2.59 2.63 v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 rising edge 2.85 2.92 2.97 v borhyst (2) bor hysteresis - - 100 - mv t rsttempo (2)(3) por reset timing - 0.5 1.5 3.0 ms electrical characteristics stm32f410x8/b 58/142 docid028094 rev 5 6.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consum ption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at vdd or vss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted to both f hclk frequency and vdd ranges (refer to table 16: features depending on the operating power supply range ). ? the voltage scaling is adjusted to f hclk frequency as follows: ? scale 3 for f hclk 64 mhz ? scale 2 for 64 mhz < f hclk 84 mhz ? scale 1 for 84 mhz < f hclk 100 mhz ? the system clock is hclk, f pclk1 = f hclk /2, and f pclk2 = f hclk . ? external clock is 4 mhz and pll is on except if it is explicitly mentioned. ? the maximum values are obtained for v dd = 3.6 v and a maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. i rush (2) in-rush current on voltage regulator power- on (por or wakeup from standby) - - 160 200 ma e rush (2) in-rush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 125 c, i rush = 171 ma for 31 s --5.4c 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 2. guaranteed by design. 3. the reset timing is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is fetched by the user application code. table 20. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit docid028094 rev 5 59/142 stm32f410x8/b electrical characteristics 118 table 21. typical and maximum current consum ption, code with data processing (art accelerator disabled) running from sram - v dd = 1.7 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 17.4 18.3 (5) 19.1 19.4 (6) 20.2 (5) ma 84 s2 168 14.1 14.8 (5) 15.4 15.8 (6) 16.6 (5) 64 s3 128 9.8 10.3 (5) 10.7 11.0 (6) 11.7 (5) 50 s3 100 7.7 8.1 8.5 8.8 9.5 25 s3 100 4.1 4.4 4.7 5.0 5.7 20 s3 160 3.5 3.8 4.1 4.4 5.1 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 2.5 2.6 2.9 3.2 4.0 1 s3 off 0.4 0.5 0.8 1.2 2.0 external clock, all peripherals disabled (3) 100 s1 200 11.8 12.5 12.9 13.3 14.1 84 s2 168 9.6 10.1 10.4 10.8 11.6 64 s3 128 6.7 7.2 7.4 7.7 8.4 50 s3 100 5.3 5.6 5.9 6.2 6.9 25 s3 100 2.9 3.1 3.3 3.7 4.4 20 s3 160 2.5 2.7 2.9 3.2 3.9 hsi, pll off, all peripherals disabled (3) 16 s3 off 1.7 1.9 2.1 2.4 3.2 1 s3 off 0.3 0.4 0.7 1.1 1.9 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for t he analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) 5. guaranteed by tests in production. 6. guaranteed by test in production for temperature range 7 salestypes only. electrical characteristics stm32f410x8/b 60/142 docid028094 rev 5 table 22. typical and maximum current consum ption, code with data processing (art accelerator disabled) running from sram - v dd = 3.6 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 17.7 19.1 (5) 19.3 19.7 (6) 20.5 (5) ma 84 s2 168 14.4 15.3 (5) 15.7 16.0 (6) 16.8 (5) 64 s3 128 10.1 10.6 (5) 11.0 11.3 (6) 12.0 (5) 50 s3 100 8.0 8.4 8.8 9.1 9.8 25 s3 100 4.4 4.7 4.9 5.2 5.9 20 s3 160 3.8 4.1 4.3 4.6 5.3 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 2.5 2.6 2.9 3.2 4.0 1 s3 off 0.4 0.5 0.8 1.2 2.0 external clock, all peripherals disabled (3) 100 s1 200 12.1 13.1 (5) 13.1 13.5 (6) 14.3 (5) 84 s2 168 9.8 10.6 (5) 10.7 11.0 (6) 11.8 (5) 64 s3 128 7.0 7.4 (5) 7.6 7.9 (6) 8.6 (5) 50 s3 100 5.6 5.9 6.1 6.4 7.2 25 s3 100 3.1 3.3 3.5 3.9 4.8 20 s3 160 2.8 3.0 3.2 3.5 4.4 hsi, pll off, all peripherals disabled (3) 16 s3 off 1.7 1.8 2.1 2.4 3.3 1 s3 off 0.4 0.4 0.7 1.1 1.8 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) 5. guaranteed by tests in production. 6. guaranteed by test in production for temperature range 7 salestypes only. docid028094 rev 5 61/142 stm32f410x8/b electrical characteristics 118 table 23. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory- v dd = 1.7 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 15.7 16.5 16.5 16.9 17.8 ma 84 s2 168 12.7 13.3 13.4 13.8 14.6 64 s3 128 8.8 9.3 9.4 9.7 10.6 50 s3 100 7.0 7.4 7.5 7.8 8.6 25 s3 100 3.9 4.1 4.3 4.7 5.6 20 s3 160 3.4 3.6 3.8 4.2 5.1 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 2.4 2.5 2.8 3.2 4.1 1 s3 off 0.6 0.7 1.0 1.4 2.3 external clock, all peripherals disabled (3) 100 s1 200 10.1 10.7 10.8 11.2 12.0 84 s2 168 8.2 8.6 8.7 9.1 10.0 64 s3 128 5.7 6.1 6.2 6.6 7.4 50 s3 100 4.6 4.9 5.0 5.4 6.3 25 s3 100 2.6 2.8 3.0 3.4 4.3 20 s3 160 2.4 2.5 2.8 3.1 4.0 hsi, pll off, all peripherals disabled (3) 16 s3 off 1.7 1.8 2.1 2.4 3.3 1 s3 off 0.6 0.6 1.0 1.4 2.2 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1. 6 ma per adc for the analog part. in appl ications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) electrical characteristics stm32f410x8/b 62/142 docid028094 rev 5 table 24. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled except prefetch) running from flash memory - v dd = 3.6 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 16.3 17.3 (5) 17.1 17.5 (6) 18.4 (5) ma 84 s2 168 13.2 14.1 14.0 14.3 15.2 64 s3 128 9.3 10.0 9.9 10.2 11.1 50 s3 100 7.4 8.0 8.0 8.3 9.2 25 s3 100 4.2 4.7 4.8 5.0 5.9 20 s3 160 3.7 4.2 4.3 4.6 5.5 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 2.4 2.8 3.0 3.4 4.3 1 s3 off 0.6 1.0 1.2 1.5 2.4 external clock, all peripherals disabled (3) 100 s1 200 10.6 11.4 (5) 11.4 11.7 (6) 12.6 (5) 84 s2 168 8.7 9.4 9.3 9.7 10.6 64 s3 128 6.2 6.8 6.8 7.1 7.9 50 s3 100 5.0 5.5 5.5 5.8 6.8 25 s3 100 2.9 3.4 3.5 3.8 4.7 20 s3 160 2.7 3.1 3.2 3.5 4.4 hsi, pll off, all peripherals disabled (3) 16 s3 off 1.7 2.1 2.3 2.6 3.5 1 s3 off 0.6 0.9 1.1 1.5 2.4 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) 5. guaranteed by tests in production. 6. guaranteed by test in production on temperature range 7 salestypes only. docid028094 rev 5 63/142 stm32f410x8/b electrical characteristics 118 table 25. typical and maximum current consumpt ion in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 3.6 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 24.7 26.3 26.5 27.0 28.0 ma 84 s2 168 21.6 23.0 23.2 23.7 24.7 64 s3 128 15.9 17.0 17.1 17.6 18.6 50 s3 100 13.1 14.2 14.3 14.7 15.7 25 s3 100 7.5 8.2 8.3 8.7 9.7 20 s3 160 6.5 7.1 7.2 7.5 8.5 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 4.7 5.3 5.5 5.9 6.9 1 s3 off 0.8 1.2 1.6 1.9 2.9 external clock, all peripherals disabled (3) 100 s1 200 19.1 20.5 20.7 21.3 22.3 84 s2 168 17.1 18.3 18.6 19.1 20.1 64 s3 128 12.8 13.8 14.0 14.5 15.5 50 s3 100 10.7 11.7 11.8 12.2 13.2 25 s3 100 6.3 7.0 7.1 7.4 8.3 20 s3 160 5.4 6.0 6.2 6.5 7.4 hsi, pll off, all peripherals disabled (3) 16 s3 off 4.0 4.5 5.0 5.1 6.0 1 s3 off 0.8 1.1 1.5 1.8 2.7 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) electrical characteristics stm32f410x8/b 64/142 docid028094 rev 5 table 26. typical and maximum current consumpt ion in run mode, code with data processing (art accelerator disabled) running from flash memory - v dd = 1.7 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 24.2 26.2 25.7 26.5 27.6 ma 84 s2 168 20.0 21.8 21.4 22.1 23.1 64 s3 128 15.8 17.2 17.0 17.7 18.7 50 s3 100 13.3 16.5 14.4 15.0 16.0 25 s3 100 7.5 9.5 8.3 8.8 9.8 20 s3 160 6.7 8.2 7.3 7.7 8.6 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 5.1 6.4 5.7 6.2 7.1 1 s3 off 0.8 1.0 1.3 1.7 2.6 external clock, all peripherals disabled (3) 100 s1 200 18.6 23.0 23.4 23.9 24.9 84 s2 168 15.5 19.3 19.9 20.4 21.4 64 s3 128 12.7 16.1 16.7 17.0 18.0 50 s3 100 10.9 13.9 14.3 14.7 15.7 25 s3 100 6.3 8.1 8.4 8.7 9.7 20 s3 160 5.6 7.2 7.3 7.6 8.4 hsi, pll off, all peripherals disabled (3) 16 s3 off 4.3 5.5 5.8 6.2 7.1 1 s3 off 0.8 1.0 1.3 1.6 2.5 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in appl ications, this cons umption occurs only while the adc is on (adon bit is set in the adc_cr2 register) docid028094 rev 5 65/142 stm32f410x8/b electrical characteristics 118 table 27. typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory - v dd = 3.6 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in run mode external clock, all peripherals enabled (3)(4) 100 s1 200 27.1 28.9 28.9 29.5 30.5 ma 84 s2 168 23.2 24.8 24.9 25.5 26.5 64 s3 128 17.0 18.3 18.4 18.8 19.8 50 s3 100 13.6 14.7 14.7 15.2 16.2 25 s3 100 7.5 8.2 8.3 8.7 9.7 20 s3 160 6.5 7.1 7.2 7.5 8.5 hsi, pll off, all peripherals enabled (3)(4) 16 s3 off 4.7 5.3 5.5 5.9 6.9 1 s3 off 0.8 1.2 1.4 1.8 2.8 external clock, all peripherals disabled (3) 100 s1 200 21.5 23.0 23.2 23.8 24.8 84 s2 168 18.7 20.0 20.3 20.8 21.8 64 s3 128 14.0 15.1 15.2 15.7 16.7 50 s3 100 11.2 12.2 12.3 12.7 13.7 25 s3 100 6.3 7.0 7.1 7.4 8.4 20 s3 160 5.4 6.0 6.2 6.5 7.5 hsi, pll off, all peripherals disabled (3) 16 s3 off 4.0 4.5 4.8 5.1 6.1 1 s3 off 0.8 1.1 1.4 1.7 2.7 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) electrical characteristics stm32f410x8/b 66/142 docid028094 rev 5 table 28. typical and maximum current consumption in sleep mode - v dd = 3.6 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in sleep mode all peripherals enabled (3)(4) , external clock, pll on, flash memory in deep power down mode 100 s1 200 8.0 8.2 (5) 9.0 9.4 (6) 10.2 (5) ma 84 s2 168 6.5 6.7 7.4 7.7 8.5 64 s3 128 4.6 4.7 5.2 5.5 6.3 50 s3 100 3.7 3.9 4.3 4.6 5.4 25 s3 100 2.2 2.3 2.6 2.9 3.8 20 s3 160 2.1 2.2 2.5 2.8 3.6 all peripherals enabled (3)(4) , hsi, pll off, flash memory in deep power down mode 16 s3 off 1.1 1.2 1.5 1.9 2.7 1 s3 off 0.3 0.4 0.7 1.1 1.9 all peripherals enabled (3)(4) , external clock, pll on, flash memory on 100 s1 200 8.4 8.7 9.5 9.9 10.7 84 s2 168 6.9 7.1 7.7 8.1 8.9 64 s3 128 4.9 5.1 5.5 5.9 6.7 50 s3 100 4.0 4.2 4.6 4.9 5.7 25 s3 100 2.5 2.6 2.9 3.2 4.0 20 s3 160 2.4 2.5 2.7 3.1 3.9 all peripherals enabled (3) , hsi, pll off, flash memory on 16 s3 off 1.4 1.4 1.8 2.2 3.0 1 s3 off 0.6 0.6 1.0 1.3 2.0 docid028094 rev 5 67/142 stm32f410x8/b electrical characteristics 118 i dd (continued) supply current in sleep mode (continued) all peripherals disabled, external clock, pll on, flash memory in deep power down mode 100 s1 200 2.2 2.3 (5) 2.6 3.0 (6) 3.8 (5) ma 84 s2 168 1.8 1.9 2.2 2.6 3.4 64 s3 128 1.4 1.5 1.8 2.1 2.9 50 s3 100 1.2 1.3 1.6 1.9 2.7 25 s3 100 0.9 1.0 1.3 1.7 2.5 20 s3 160 1.0 1.2 1.4 1.7 2.5 all peripherals disabled, hsi, pll off, flash memory in deep power down mode 16 s3 off 0.3 0.4 0.7 1.1 1.9 1 s3 off 0.3 0.3 0.7 1.0 1.8 all peripherals disabled, external clock, pll on, flash memory on 100 s1 200 2.6 2.7 3.0 3.4 4.2 84 s2 168 2.2 2.3 2.6 3.0 3.8 64 s3 128 1.8 1.9 2.1 2.5 3.3 50 s3 100 1.5 1.6 1.9 2.2 3.1 25 s3 100 1.2 1.4 1.6 2.0 2.8 20 s3 160 1.3 1.4 1.7 2.0 2.8 all peripherals disabled, hsi, pll off, flash memory in deep power down mode 16 s3 off 0.6 0.6 1.0 1.3 2.0 1 s3 off 0.5 0.6 0.9 1.3 2.0 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for t he analog part. in applications, th is consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) 5. guaranteed by tests in production. 6. guaranteed by test in production on temperature range 7 salestypes only. table 28. typical and maximum current consumption in sleep mode - v dd = 3.6 v (continued) symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c electrical characteristics stm32f410x8/b 68/142 docid028094 rev 5 table 29. typical and maximum current consumption in sleep mode - v dd = 1.7 v symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c i dd supply current in sleep mode all peripherals enabled (3) (4) , external clock, pll on, flash memory in deep power down mode 100 s1 200 7.7 7,9 8,8 9,2 10.0 ma 84 s2 168 6.2 6,4 7,1 7,5 8.3 64 s3 128 4.3 4,5 5,0 5,3 6.1 50 s3 100 3.4 3,6 4,0 4,4 5.2 25 s3 100 2.0 2,1 2,4 2,7 3.5 20 s3 160 1.8 1,9 2,3 2,6 3.4 all peripherals enabled (3)(4) , hsi, pll off, flash memory in deep power down mode 16 s3 off 1.1 1,2 1,5 1,9 2.7 1 s3 off 0.3 0,4 0,7 1,0 1.8 all peripherals enabled (3)(4) , external clock, pll on, flash memory on 100 s1 200 8.1 8,4 9,3 9,7 10.5 84 s2 168 6.6 6,8 7,5 7,9 8.7 64 s3 128 4.7 4,8 5,4 5,7 6.5 50 s3 100 3.8 3,9 4,4 4,7 5.5 25 s3 100 2.3 2,4 2,7 3,1 3.9 20 s3 160 2.1 2,2 2,6 2,9 3.7 all peripherals enabled (3)(4) , hsi, pll off, flash memory on 16 s3 off 1.4 1,5 1,8 2,2 3.0 1 s3 off 0.5 0,6 1,0 1,3 2.0 docid028094 rev 5 69/142 stm32f410x8/b electrical characteristics 118 i dd (continued) supply current in sleep mode (continued) all peripherals disabled, external clock, pll on, flash memory in deep power down mode 100 s1 200 1.9 2,0 2,4 2,7 3.5 ma 84 s2 168 1.6 1,7 2,0 2,4 3.2 64 s3 128 1.1 1,2 1,5 1,9 2.7 50 s3 100 0.9 1,0 1,3 1,7 2.5 25 s3 100 0.7 0,8 1,1 1,4 2.2 20 s3 160 0.8 0,8 1,2 1,5 2.3 all peripherals disabled, hsi, pll off, flash memory in deep power down mode 16 s3 off 0.3 0,4 0,7 1,0 1.8 1 s3 off 0.2 0,3 0,6 1,0 1.8 all peripherals disabled, external clock, pll on, flash memory on 100 s1 200 2.3 2,4 2,9 3,3 4.0 84 s2 168 2.0 2,1 2,4 2,8 3.6 64 s3 128 1.5 1,6 1,9 2,3 3.1 50 s3 100 1.3 1,4 1,7 2,0 2.8 25 s3 100 1.0 1,1 1,4 1,7 2.5 20 s3 160 1.0 1,2 1,5 1,8 2.6 all peripherals disabled, hsi, pll off, flash memory in deep power down mode 16 s3 off 0.6 0,6 1,0 1,4 2.1 1 s3 off 0.5 0,6 0,9 1,3 2.0 1. refer to table 44 and rm0401 for the possible pll vco setting 2. guaranteed by characterization, unless otherwise specified. 3. when the adc is on (adon bit set in adc_cr2), an additional power consumption of 1.6 ma must be added. 4. add an additional power consumption of 1.6 ma per adc for the analog part. in appl ications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register) table 29. typical and maximum current consumption in sleep mode - v dd = 1.7 v (continued) symbol parameter conditions f hclk (mhz) voltage scale pll vco (mhz) (1) typ max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c t a = 125 c electrical characteristics stm32f410x8/b 70/142 docid028094 rev 5 table 30. typical and maximum current consumptions in stop mode - v dd = 1.7 v symbol conditions typ max unit t a = 25 c t a = 25 c (1) t a = 85 c t a = 105 c (1) t a = 125 c (1) i dd_stop flash in stop mode, all oscillators off, no independent watchdog main regulator usage 105.6 117.1 385.1 665.7 1270.0 a low power regulator usage 39.5 48.7 287.5 548.4 1070.0 flash in deep power down mode, all oscillators off, no independent watchdog main regulator usage 77.8 87.5 351.3 630.1 1222.0 low power regulator usage 11.0 20.0 254.2 512.0 1006.0 low power low voltage regulator usage 6.1 13.6 217.0 442.5 941.0 1. guaranteed by characterization. table 31. typical and maximum current consumption in stop mode - v dd =3.6 v symbol conditions typ max unit t a = 25 c t a = 25 c (1) t a = 85 c t a = 105 c (1) t a = 125 c (1) i dd_stop flash in stop mode, all oscillators off, no independent watchdog main regulator usage 108.6 126 (2) 392.8 675.4 (3) 1280.0 (2) a low power regulator usage 41.03 50.31 (2) 290.9 554.2 (3) 1077.0 (2) flash in deep power down mode, all oscillators off, no independent watchdog main regulator usage 80.32 94.0 (2) 357.0 639.5 (3) 1232.0 (2) low power regulator usage 12.41 21.5 (2) 258.1 518.1 (3) 1010.0 (2) low power low voltage regulator usage 7.53 15.2 (2) 221.6 449.2 (3) 947.0 (2) 1. guaranteed by characterization. 2. guaranteed by tests in production. 3. guaranteed by test in production on temperature range 7 salestypes only. table 32. typical and maximum current consumption in standby mode - v dd = 1.7 v symbol parameter conditions typ max unit t a = 25 c t a = 25 c (1) t a = 85 c t a = 105 c (1) t a = 125 c (1) i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 2.1 2.9 6.5 18.2 60.0 a rtc and lse off 1.2 1.9 5.5 17.1 59.0 1. guaranteed by characterization, unless otherwise specified. docid028094 rev 5 71/142 stm32f410x8/b electrical characteristics 118 table 33. typical and maximum current consumption in standby mode - v dd = 3.6 v symbol parameter conditions typ max uni t t a = 25 c t a = 25 c (1) t a = 85 c t a = 105 c (1) t a = 125 c (1) i dd_stby supply current in standby mode low-speed oscillator (lse) and rtc on 3.4 4.3 8.9 22.8 65.0 a rtc and lse off 2.5 3.3 (2) 7.8 21.6 (3) 64.0 (2) 1. guaranteed by characterization, unless otherwise specified. 2. guaranteed by tests in production. 3. guaranteed by test in production on temperature range 7 salestypes only. table 34. typical and maximum current consumptions in v bat mode (lse and rtc on, lse low- drive mode) symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c t a = 125 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current low-speed oscillator (lse in low-drive mode) and rtc on 0.7 0.8 1.1 2.8 4.2 5.6 a low-speed oscillator (lse in high-drive mode) and rtc on 1.4 1.6 1.9 4.2 7.0 8.6 rtc and lse off 0.1 0.1 0.1 2.0 4.0 5.8 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed by characterization. electrical characteristics stm32f410x8/b 72/142 docid028094 rev 5 figure 16. typical v bat current consumption (lse and rtc on/lse oscillator in ?low power? mode selection figure 17. typical v bat current consumption (lse and rtc on/lse oscillator in ?high-drive? mode selection) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 55: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt 0 6 9 , ' ' b 9 % $ 7 ? $ 7 h p s h u d w x u h ? & 0 6 9 , ' ' b 9 % $ 7 ? $ 7 h p s h u d w x u h ? & docid028094 rev 5 73/142 stm32f410x8/b electrical characteristics 118 trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = electrical characteristics stm32f410x8/b 74/142 docid028094 rev 5 table 35. switching output i/o current consumption symbol parameter conditions (1) 1. cs is the pcb board capacitance including the pad pin. cs = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit iddio i/o switching current v dd = 3.3 v c = c int 2 mhz 0.05 ma 8 mhz 0.15 25 mhz 0.45 50 mhz 0.85 60 mhz 1.00 84 mhz 1.40 90 mhz 1.67 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 8 mhz 0.35 25 mhz 1.05 50 mhz 2.20 60 mhz 2.40 84 mhz 3.55 90 mhz 4.23 v dd = 3.3 v c ext =10 pf c = c int + c ext + c s 2 mhz 0.20 8 mhz 0.65 25 mhz 1.85 50 mhz 2.45 60 mhz 4.70 84 mhz 8.80 90 mhz 10.47 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.25 8 mhz 1.00 25 mhz 3.45 50 mhz 7.15 60 mhz 11.55 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.32 8 mhz 1.27 25 mhz 3.88 50 mhz 12.34 docid028094 rev 5 75/142 stm32f410x8/b electrical characteristics 118 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? the art accelerator is on. ? voltage scale 2 mode selected, internal digital voltage v12 = 1.26 v. ? hclk is the system clock at 100 mhz. f pclk1 = f hclk /2, and f pclk2 = f hclk . the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature is 25 c and v dd =3.3 v. table 36. peripheral current consumption peripheral i dd (typ) unit voltage scale1 voltage scale2 voltage scale3 ahb 1 (up to 100 mhz) gpioa 1.68 1.62 1.42 a/mhz gpiob 1.67 1.60 1.41 gpioc 1.63 1.56 1.39 gpioh 0.61 0.61 0.52 crc 0.31 0.32 0.25 dma1 (1) 1.67n + 3.12 1.60n + 2.96 1.43n + 2.64 dma2 (1) 1.59n + 2.83 1.52n + 2.65 1.36n + 2.41 rng 0.90 0.88 0.75 apb1 (up to 50 mhz) apb1 to ahb 0,78 0,74 0,63 a/mhz tim5 13,38 12,76 11,41 tim6 2,14 1,98 1,75 lptim 8,22 7,88 7,06 wwdg 0,64 0,64 0,56 spi2/i2s2 2,42 2,33 2,06 usart2 3,38 3,29 2,91 i2c1 3,46 3,33 2,97 i2c2 3,50 3,31 2,97 i2c4 4,82 4,64 4,09 pwr 0,66 0,64 0,62 dac 0,84 0,81 0,78 electrical characteristics stm32f410x8/b 76/142 docid028094 rev 5 apb2 (up to 100 mhz) apb2 to ahb 0,22 0,19 0,17 a/mhz tim1 6,62 6,36 5,66 usart1 3,19 3,10 2,77 usart6 3,10 2,99 2,66 adc1 3,35 3,25 2,88 spi1/i2s1 1,82 1,77 1,58 syscfg 0,83 0,81 0,72 exti 0,92 0,88 0,80 tim9 2,90 2,81 2,48 tim11 2,13 2,06 1,81 spi5/i2s5 1,88 1,83 1,59 bus matrix 1.91 1.82 1.64 1. valid if all the dma streams are activated (p lease refer to the reference manual rm0401). table 36. peripheral current consumption (continued) peripheral i dd (typ) unit voltage scale1 voltage scale2 voltage scale3 docid028094 rev 5 77/142 stm32f410x8/b electrical characteristics 118 6.3.7 wakeup time from low-power modes the wakeup times given in table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. figure 18. low-power mode wakeup all timings are derived from tests performed under ambient temperature and v dd =3.3 v. 5 h j x o d w r u u d p s x s + 6 , u h v w d u w ) o d v k v w r s h [ l w & 3 8 u h v w d u w : d n h x s i u r p 6 w r s p r g h p d l q u h j x o d w r u 5 h j x o d w r u u d p s x s + 6 , u h v w d u w ) o d v k ' h h s 3 g u h f r y h u \ & 3 8 u h v w d u w : d n h x s i u r p 6 w r s p r g h p d l q u h j x o d w r u i o d v k l q ' h h s s r z h u g r z q p r g h 5 h j x o d w r u u d p s x s + 6 , u h v w d u w ) o d v k v w r s h [ l w & 3 8 u h v w d u w : d n h x s i u r p 6 w r s u h j x o d w r u l q o r z s r z h u p r g h 5 h j x o d w r u u d p s x s + 6 , u h v w d u w & 3 8 u h v w d u w : d n h x s i u r p 6 w r s u h j x o d w r u l q o r z s r z h u p r g h i o d v k l q ' h h s s r z h u g r z q p r g h 5 h j x o d w r u u h v w d u w + 6 , u h v w d u w & 3 8 u h v w d u w : d n h x s i u r p 6 w d q g e \ p r g h & 3 8 u h v w d u w : d n h x s i u r p 6 o h h s d q g ) o d v k l q ' h h s s r z h u g r z q 0 6 9 ) o d v k ' h h s 3 g u h f r y h u \ 2 s w l r q e \ w h v d u h q r w u h o r d g h g 2 s w l r q e \ w h v d u h q r w u h o r d g h g ) o d v k ' h h s 3 g u h f r y h u \ 2 s w l r q e \ w h v o r d g l q j ) o d v k ' h h s 3 g u h f r y h u \ 2 s w l r q e \ w h v d u h q r w u h o r d g h g 2 s w l r q e \ w h v d u h q r w u h o r d g h g 5 h j x o d w r u 2 ) ) 2 s w l r q e \ w h v d u h q r w u h o r d g h g 5 h j x o d w r u 2 1 electrical characteristics stm32f410x8/b 78/142 docid028094 rev 5 6.3.8 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 55 . however, the recommended clock input waveform is shown in figure 19 . the characteristics given in table 38 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 15 . table 37. low-power mode wakeup timings (1) symbol parameter condi tions min typ max unit t wusleep (2) wakeup from sleep mode --46 cpu clock cycles t wusleepfdsm (2) flash memory in deep power down mode - - 40,0 s t wustop (2) wakeup from stop mode, code execution from flash memory main regulator - 12.9 15.0 main regulator, flash memory in deep power down mode - 104.9 115.0 regulator in low-power mode (3) - 20.8 25.0 regulator in low-power mode, flash memory in deep power down mode - 112.9 120.0 wakeup from stop mode, code execution from ram main regulator, flash memory in stop or deep power down mode -4.97.0 regulator in low-power mode, flash memory in stop or deep power down mode (3) - 12.8 20.0 t wustdby (2)(4) wakeup from standby mode - - 316.8 350.0 t wuflash wakeup of flash memory fr om flash_stop mode - - 10.0 wakeup of flash memory from flash deep power down mode - - 40.0 1. guaranteed by characterization. 2. the wakeup times are measured from the wakeup event to the po int in which the application c ode reads the first instruction. 3. the specification is valid for wakeup fr om regulator in low power mode or in low power low voltage mode, since the timing difference is negligible. 4. t wustdby maximum value is given at - 40 c. docid028094 rev 5 79/142 stm32f410x8/b electrical characteristics 118 low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 55 . however, the recommended clock input waveform is shown in figure 20 . the characteristics given in table 39 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 15 . table 38. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) - 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) --5-pf ducy (hse) duty cycle - 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 39. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) --5-pf ducy (lse) duty cycle - 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. electrical characteristics stm32f410x8/b 80/142 docid028094 rev 5 figure 19. high-speed external clock source ac timing diagram figure 20. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , d l 2 6 & b , 1 ( [ w h u q d o 6 7 0 ) f o r f n v r x u f h 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / docid028094 rev 5 81/142 stm32f410x8/b electrical characteristics 118 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-f requency applications, and selected to match the requirements of the crystal or resonator (see figure 21 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 21. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 41 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 40. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design. symbol parameter condi tions min typ max unit f osc_in oscillator frequency - 4 - 26 mhz r f feedback resistor - - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 , c l =5 pf @25 mhz -450- a v dd =3.3 v, esr= 30 , c l =10 pf @25 mhz -530- g m_crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse) (2) 2. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms d l 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( & / 5 ) 6 7 0 ) 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / electrical characteristics stm32f410x8/b 82/142 docid028094 rev 5 the lse high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . for information about the lse high-power mode, refer to the reference manual rm0401. figure 22. typical applicati on with a 32.768 khz crystal table 41. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design. symbol parameter conditions min typ max unit r f feedback resistor - - 18.4 - m i dd lse current consumption low-power mode (default) --1 a high-drive mode - - 3 g m _crit_max maximum critical crystal g m startup, low-power mode - - 0.56 a/v startup, high-drive mode - - 1.50 t su(lse) (2) 2. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is guaranteed by characterizati on. it is measured for a standard crystal resonator and it can vary signi ficantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s d l 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / 5 ) 6 7 0 ) n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q & / docid028094 rev 5 83/142 stm32f410x8/b electrical characteristics 118 6.3.9 internal clock source characteristics the parameters given in table 42 and table 43 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 15 . high-speed internal (hsi) rc oscillator l figure 23. acc hsi versus temperature 1. guaranteed by characterization. table 42. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 125 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. guaranteed by design. --1% factory- calibrated t a = ?40 to 125 c (3) 3. guaranteed by characterization. ?8 - 5.5 % t a = ?10 to 85 c (3) ?4 - 4 % t a = 25 c (4) 4. factory calibrated non-soldered parts. ?1 - 1 % t su(hsi) (2) hsi oscillator startup time --2.24s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a - 3 6 - i n - a x 4 y p i c a l 4 ! ? # ! # # ( 3 ) electrical characteristics stm32f410x8/b 84/142 docid028094 rev 5 low-speed internal (lsi) rc oscillator figure 24. acc lsi versus temperature 6.3.10 pll characteristics the parameters given in table 44 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 15 . table 43. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 125 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 44. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) -0.95 (2) 12.10mhz f pll_out pll multiplier output clock - 24 - 100 mhz f pll48_out 48 mhz pll multiplier output clock - - 48 75 mhz f vco_out pll vco output - 100 - 432 mhz docid028094 rev 5 85/142 stm32f410x8/b electrical characteristics 118 t lock pll lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 100 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - i dd(pll) (4) pll power consumption on vdd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of two plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization. table 44. main pll characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f410x8/b 86/142 docid028094 rev 5 6.3.11 pll spread spectrum clo ck generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 51: emi characteristics for lqfp64 ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation dep th (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 45. sscg parameter constraints symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep (modulation period) * (increment step) - - 2 15 -1 - 1. guaranteed by design. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == docid028094 rev 5 87/142 stm32f410x8/b electrical characteristics 118 figure 25 and figure 26 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 25. pll output clock waveforms in center spread mode figure 26. pll output clock waveforms in down spread mode 6.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 125 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e m d a i m d ) u h t x h q f \ 3 / / b 2 8 7 7 l p h ) w p r g h [ w p r g h [ p g d l e table 46. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - electrical characteristics stm32f410x8/b 88/142 docid028094 rev 5 table 47. flash memory programming symbol parameter conditions min (1) typ max (1) 1. guaranteed by characterization. unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) 2. the maximum programming time is m easured after 100k erase operations. s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t me mass erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.42.8 program/erase parallelism (psize) = x 32 -12 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v table 48. flash memory programming with v pp voltage symbol parameter conditions min (1) typ max (1) unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 3.50 - s v prog programming voltage - 2.7 - 3.6 v v pp v pp voltage range - 7 - 9 v i pp minimum current sunk on the v pp pin -10--ma t vpp (3) cumulative time during which v pp is applied - - - 1 hour docid028094 rev 5 89/142 stm32f410x8/b electrical characteristics 118 6.3.13 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. 1. guaranteed by design. 2. the maximum programming time is measured after 100k erase operations. 3. v pp should only be connected during programming/erasing. table 49. flash memory endurance and data retention symbol parameter conditions value unit min (1) n end endurance t a = - 40 to +85 c (6 suffix versions) t a = - 40 to +105 c (7 suffix versions) t a = - 40 to +125 c (3 suffix versions) 10 kcycle tret data retention 1 kcycle (2) at t a = 85 c 30 years 1 kcycle (2) at t a = 105 c 10 1 kcycle (2) at t a = 125 c 3 10 kcycle (2) at t a = 55 c 20 1. guaranteed by characterization. 2. cycling performed over the whole temperature range. table 50. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25 c, f hclk = 100 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25 c, f hclk = 100 mhz, conforms to iec 61000-4-4 4a electrical characteristics stm32f410x8/b 90/142 docid028094 rev 5 in noisy environments, it is recommended to avoid pin exposition to disturbances. the pins showing a middle range robustness are pa14 and pa15. as a consequence, it is recommended to add a serial resistor (1 k ? maximum) located as close as possible to the mcu pins exposed to noise (connected to tracks longer than 50 mm on pcb). designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. table 51. emi characteristics for lqfp64 symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 8/100 mhz s emi peak level v dd = 3.6 v, t a = 25 c, conforming to iec61967-2 0.1 to 30 mhz 10 dbv 30 to 130 mhz 11 130 mhz to 1 ghz 5 sae emi level 2.5 - docid028094 rev 5 91/142 stm32f410x8/b electrical characteristics 118 6.3.14 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 6.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. table 52. esd absolute maximum ratings (1) symbol ratings conditions class maximum value (2) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to ansi/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to ansi/esd stm5.3.1 ufqfpn48 4 500 wlcsp36 3 250 lqfp48 4 500 lqpf64 4 500 ufbga64 tbd tbd 1. tbd stands for ?to be defined?. 2. guaranteed by characterization. table 53. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +125 c conforming to jesd78a ii level a electrical characteristics stm32f410x8/b 92/142 docid028094 rev 5 functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failure (f or example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 54 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 55 are derived from tests performed under the conditions summarized in table 15 . all i/os are cmos and ttl compliant. table 54. i/o current in jection susc eptibility (1) 1. na = not applicable . symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin - 0 na ma injected current on nrst pin - 0 na injected current on pb3, pb4, pb5, pb6, pb7, pb8, pb9, pc13, pc14, pc15, ph1, pdr_on, pc0, pc1, pc2, pc3 - 0 na injected current on any other ft pin - 5 na injected current on any other pins - 5 + 5 table 55. i/o static characteristics symbol parameter conditions min typ max unit v il ft, tc and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.3v dd (1) v boot0 i/o input low level voltage 1.75 v v dd 3.6 v, - 40 c t a 125 c -- 0.1v dd +0.1 (2) 1.7 v v dd 3.6 v, 0 c t a 125 c -- docid028094 rev 5 93/142 stm32f410x8/b electrical characteristics 118 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft and tc i/os is shown in figure 27 . v ih ft, tc and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.7v dd (1) -- v boot0 i/o input high level voltage 1.75 v v dd 3.6 v, -40 c t a 125 c 0.17v dd + 0.7 (2) -- 1.7 v v dd 3.6 v, 0 c t a 125 c v hys ft, tc and nrst i/o input hysteresis 1.7 v v dd 3.6 v - 10% v dd (3) -v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, - 40 c t a 125 c -100 -mv 1.7 v v dd 3.6 v, 0 c t a 125 c i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft/tc input leakage current (5) v in = 5 v - - 3 r pu weak pull-up equivalent resistor (6) all pins except for pa10 (otg_fs_id) v in = v ss 30 40 50 k pa10 (otg_fs_id) - 7 10 14 r pd weak pull-down equivalent resistor (7) all pins except for pa10 (otg_fs_id) v in = v dd 30 40 50 pa10 (otg_fs_id) - 7 10 14 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by tests in production. 2. guaranteed by design. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if negat ive current is injected on adjacent pins, refer to table 54: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative curr ent is injected on adjacent pins.refer to table 54: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a true resistance in se ries with a switchable nmos. th is nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger sw itching levels. guaranteed by characterization. table 55. i/o static characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics stm32f410x8/b 94/142 docid028094 rev 5 figure 27. ft/tc i/o in put characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 13 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 13 ). output voltage levels unless otherwise specified, the parameters given in table 56 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15 . all i/os are cmos and ttl compliant. 0 6 9 9 ' ' 9 9 , / 9 , + 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , / p d [ 9 ' ' % d v h g r q ' h v l j q v l p x o d w l r q v 9 , / p d [ 9 ' ' 7 7 / u h t x l u h p h q w 9 , + p l q 9 7 7 / u h t x l u h p h q w 9 , / p d [ 9 $ u h d q r w g h w h u p l q h g % d v h g r q ' h v l j q v l p x o d w l r q v 9 , + p l q 9 ' ' docid028094 rev 5 95/142 stm32f410x8/b electrical characteristics 118 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 28 and table 57 , respectively. unless otherwise specified, the parameters given in table 57 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 15 . table 56. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 13 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+8 ma 2.7 v v dd 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. guaranteed by characterization results. v v oh (3) output high level voltage for an i/o pin v dd ?1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6 v -0.4 (5) 5. guaranteed by design. v v oh (3) output high level voltage for an i/o pin v dd ?0.4 (5) - table 57. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.70 v - - 8 c l = 10 pf, v dd 1.7 v - - 4 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v - - 100 ns electrical characteristics stm32f410x8/b 96/142 docid028094 rev 5 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.70 v - - 25 mhz c l = 50 pf, v dd 1.7 v - - 12.5 c l = 10 pf, v dd 2.70 v - - 50 c l = 10 pf, v dd 1.7 v - - 20 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 2.70 v - - 6 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.70 v - - 50 (4) mhz c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 2.70 v - - 100 ( 4) c l = 10 pf, v dd 1.7 v - - 50 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.70 v - - 6 ns c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.70 v - - 4 c l = 10 pf, v dd 1.7 v - - 6 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.70 v - - 100 ( 4) mhz c l = 30 pf, v dd 1.7 v - - 50 (4) t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.70 v - - 4 ns c l = 30 pf, v dd 1.7 v - - 6 c l = 10 pf, v dd 2.70 v - - 2.5 c l = 10 pf, v dd 1.7 v - - 4 -t extipw pulse width of external signals detected by the exti controller -10--ns 1. guaranteed by characterization. 2. the i/o speed is configured using the ospeedry[1:0] bits. refer to the stm32f4xx reference manual for a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 28 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. table 57. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit docid028094 rev 5 97/142 stm32f410x8/b electrical characteristics 118 figure 28. i/o ac charac teristics definition 6.3.17 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 55 ). unless otherwise specified, the parameters given in table 58 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 15 . refer to table 55: i/o static characteristics for the values of vih and vil for nrst pin. d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 58. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resi stance in series with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. electrical characteristics stm32f410x8/b 98/142 docid028094 rev 5 figure 29. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 58 . otherwise the reset is not taken into account by the device. 6.3.18 tim time r characteristics the parameters given in table 59 are guaranteed by design. refer to section 6.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). d l f 6 7 0 ) 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o 5 h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 59. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim11 timers. 2. guaranteed by design. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 is 50 mhz and on apb2 is up to 100 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hckl, otherwise timxclk >= 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 100 mhz 1-t timxclk 11.9 - ns ahb/apbx prescaler>4, f timxclk = 100 mhz 1-t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 100 mhz 0f timxclk /2 mhz 050mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected f timxclk = 100 mhz 0.0119 780 s t max_count maximum possible count with 32-bit counter -- 65536 65536 t timxclk f timxclk = 100 mhz - 51.1 s docid028094 rev 5 99/142 stm32f410x8/b electrical characteristics 118 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 60 . refer also to section 6.3.16: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . the i 2 c bus interface supports standard mode (up to 100 khz) and fast mode (up to 400 khz). the i 2 c bus frequency can be increased up to 1 mhz. for more details about the complete solution, please contact your local st sales representative. table 60. i 2 c characteristics symbol parameter standard mode i 2 c (1)(2) 1. guaranteed by design. fast mode i 2 c (1)(2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 3450 (3) 3. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 0900 (4) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s t sp pulse width of the spikes that are suppressed by the analog filter for standard fast mode 050 (5) 050 (5) ns c b capacitive load for each bus line - 400 - 400 pf electrical characteristics stm32f410x8/b 100/142 docid028094 rev 5 figure 30. i 2 c bus ac waveforms and measurement circuit 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. 4. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. 5. the minimum width of the spikes fi ltered by the analog filter is above t sp (max) table 61. scl frequency (f pclk1 = 50 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed is 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee 0 6 y 9 5 3 , e & e x v 6 7 0 ) [ [ 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ w k 6 7 $ w z 6 & / / w z 6 & / + w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' w v x 6 7 $ w v x 6 7 2 6 7 2 3 w z 6 7 2 6 7 $ 5 3 5 6 5 6 6 7 $ 5 7 6 7 $ 5 7 6 ' $ 6 & / 9 ' ' b , & 9 ' ' b , & docid028094 rev 5 101/142 stm32f410x8/b electrical characteristics 118 table 62. scl frequency (f pclk1 = 42 mhz.,v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee electrical characteristics stm32f410x8/b 102/142 docid028094 rev 5 fmpi 2 c characteristics the fmpi2c characterist ics are described in table 63 . refer also to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). table 63. fmpi 2 c characteristics (1) - parameter standard mode fast mode fast+ mode unit min max min max min max f fmpi2cc f mpi2cclk frequency 2 - 8 - 17 16 (2) - us t w(scll) scl clock low time 4.7 - 1.3 - 0.5 - t w(sclh) scl clock high time 4.0 - 0.6 - 0.26 - t su(sda) sda setup time 0.25 - 0.10 - 0.05 - t h(sda) sda data hold time 0 - 0 - 0 - t v(sda,ack) data, ack valid time - 3.45 - 0.9 - 0.45 t r(sda) t r(scl) sda and scl rise time - 0.100 - 0.30 - 0.12 t f(sda) t f(scl) sda and scl fall time - 0.30 - 0.30 - 0.12 t h(sta) start condition hold time 4 - 0.6 - 0.26 - t su(sta) repeated start condition setup time 4.7 - 0.6 - 0.26 - t su(sto) stop condition setup time 4 - 0.6 - 0.26 - t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - 0.5 - t sp pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.09 0.05 0.09 c b capacitive load for each bus line - 400 - 400 - 550 (3) pf 1. guaranteed based on test during characterization. 2. when tr(sda,scl)<=110 ns. 3. can be limited. maximum supported value can be re trieved by referring to the following formulas: t r(sda/scl) = 0.8473 x r p x c load r p(min) = (v dd -v ol(max) ) / i ol(max) docid028094 rev 5 103/142 stm32f410x8/b electrical characteristics 118 figure 31. fmpi 2 c timing diagram and measurement circuit 0 6 y 9 5 3 , e & e x v 6 7 0 ) [ [ 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ w k 6 7 $ w z 6 & / / w z 6 & / + w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' w v x 6 7 $ w v x 6 7 2 6 7 2 3 w z 6 7 2 6 7 $ 5 3 5 6 5 6 6 7 $ 5 7 6 7 $ 5 7 6 ' $ 6 & / 9 ' ' b , & 9 ' ' b , & electrical characteristics stm32f410x8/b 104/142 docid028094 rev 5 spi interface characteristics unless otherwise specified, the parameters given in table 64 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 15 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 64. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master full duplex/receiver mode, 2.7 v < v dd < 3.6 v spi1/4/5 --42 mhz master full duplex/receiver mode, 3.0 v < v dd < 3.6 v spi1/4/5 -- 50 master transmitter mode 1.7 v < v dd < 3.6 v spi1/4/5 -- 50 master mode 1.7 v < v dd < 3.6 v spi1/2/3/4/5 -- 25 slave transmitter/full duplex mode 2.7 v < v dd < 3.6 v spi1/4/5 -- 38 (2) slave receiver mode, 1.8 v < v dd < 3.6 v spi1/4/5 --50 slave mode, 1.8 v < v dd < 3.6 v spi1/2/3/4/5 -- 25 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 % t w(sckh) t w(sckl) sck high and low time master mode, spi presc = 2 t pclk - 1.5 t pclk t pclk +1.5 ns t su(nss) nss setup time slave mode, spi presc = 2 3t pclk --ns t h(nss) nss hold time slave mode, spi presc = 2 2t pclk --ns t su(mi) data input setup time master mode 4 - - ns t su(si) slave mode 2.5 - - ns t h(mi) data input hold time master mode 7.5 - - ns t h(si) slave mode 3.5 - - ns docid028094 rev 5 105/142 stm32f410x8/b electrical characteristics 118 figure 32. spi timing diagram - slave mode and cpha = 0 t a(so ) data output access time slave mode 7 - 21 ns t dis(so) data output disable time slave mode 5 - 12 ns t v(so) data output valid time slave mode (after enable edge), 2.7 v < v dd < 3.6 v -1113ns slave mode (after enable edge), 1.7 v < v dd < 3.6 v - 11 18.5 ns t h(so) data output hold time slave mode (after enable edge), 1.7 v < v dd < 3.6 v 8--ns t v(mo) data output valid time master mode (after enable edge) - 4 6 ns t h(mo) data output hold time master mode (after enable edge) 0 - - ns 1. guaranteed by characterization. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value c an be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50% table 64. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 electrical characteristics stm32f410x8/b 106/142 docid028094 rev 5 figure 33. spi timing diagram - slave mode and cpha = 1 (1) figure 34. spi timing diagram - master mode (1) d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 docid028094 rev 5 107/142 stm32f410x8/b electrical characteristics 118 i 2 s interface characteristics unless otherwise specified, the parameters given in table 65 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 15 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i2s section of rm0401 reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of (i2sdiv/(2*i2sdiv+odd) and a maximum va lue of (i2sdiv+odd) /(2*i2sdiv+odd). f s maximum value is supported for each mode/condition. table 65. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 7 ns t h(ws) ws hold time master mode 1.5 - t su(ws) ws setup time slave mode 1.5 - t h(ws) ws hold time slave mode 3 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 2.5 - t h(sd_mr) data input hold time master receiver 7 - t h(sd_sr) slave receiver 2.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 20 t v(sd_mt) master transmitter (after enable edge) - 6 t h(sd_st) data output hold time slave transmitter (after enable edge) 8 - t h(sd_mt) master transmitter (after enable edge) 2 - 1. guaranteed by characterization. 2. the maximum value of 256xfs is 50 mhz (apb1 maximum frequency). electrical characteristics stm32f410x8/b 108/142 docid028094 rev 5 figure 35. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 36. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t docid028094 rev 5 109/142 stm32f410x8/b electrical characteristics 118 6.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in table 66 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 15 . table 66. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v ref- negative reference voltage - - 0 - f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz ---171/f adc v ain conversion voltage range (3) - 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50 ? r adc (2)(4) sampling switch resistance - - - 6 ? c adc (2) internal sample and hold capacitor --47pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s ---3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s ---2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s - 3 - 480 1/f adc t stab (2) power-up time - - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc electrical characteristics stm32f410x8/b 110/142 docid028094 rev 5 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (2) adc v ref dc current consumption in conversion mode - - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode --1.61.8ma 1. v dda minimum value of 1.7 v is possible with the us e of an external power supply supervisor (refer to section 3.15.2: internal reset off ). 2. guaranteed by characterization. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 66 . table 66. adc characteristics (continued) symbol parameter conditions min typ max unit r ain k0.5 ? () f adc c adc 2 n 2 + () ln ---------------------------------------------------------------- r adc ? = table 67. adc accuracy at f adc = 18 mhz (1) symbol parameter test conditions typ max (2) unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. 2. guaranteed by characterization. docid028094 rev 5 111/142 stm32f410x8/b electrical characteristics 118 table 68. adc accuracy at f adc = 30 mhz (1) symbol parameter tes t conditions typ max (2) unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 4 ed differential linearity error 1 2 el integral linearity error 1.5 3 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. 2. guaranteed by characterization. table 69. adc accuracy at f adc = 36 mhz (1) symbol parameter test conditions typ max (2) unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. 2. guaranteed by characterization. table 70. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion - -72 -67 1. guaranteed by characterization. table 71. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc = 36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion - -72 -70 1. guaranteed by characterization. electrical characteristics stm32f410x8/b 112/142 docid028094 rev 5 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.16 does not affect the adc accuracy. figure 37. adc accuracy characteristics 1. see also table 68 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , docid028094 rev 5 113/142 stm32f410x8/b electrical characteristics 118 figure 38. typical connecti on diagram using the adc 1. refer to table 66 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. d l 6 7 0 ) 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u electrical characteristics stm32f410x8/b 114/142 docid028094 rev 5 general pcb design guidelines power supply decoupling should be performed as shown in figure 39 . the 10 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. figure 39. power supply and reference decoupling 6.3.21 temperature sensor characteristics 0 6 y 9 6 7 0 ) ? ) q ) 9 5 ( ) 9 ' ' $ 9 5 ( ) 9 ' ' $ table 72. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed by characterization. 2. guaranteed by design. table 73. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f docid028094 rev 5 115/142 stm32f410x8/b electrical characteristics 118 6.3.22 v bat monitoring characteristics 6.3.23 embedded reference voltage the parameters given in table 75 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15 . table 74. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - - er (1) error on q ?1 - +1 % t s_vbat (2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 75. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage - 40 c < t a < + 125 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -10--s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3 v 10m v - 3 5 mv t coeff (2) temperature coefficient - - 30 50 ppm/c t start (2) startup time - - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design table 76. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b electrical characteristics stm32f410x8/b 116/142 docid028094 rev 5 6.3.24 dac electri cal characteristics table 77. dac characteristics symbol parameter conditions min typ max unit comments v dda analog supply voltage -1.7 (1) -3.6 v - v ref+ reference supply voltage -1.7 (1) -3.6vv ref+ v dda v ssa ground - 0 - 0 v - r load (2) resistive load dac output buffer on r load connected to v ssa 5- -k - r load connected to v dda 25 - - k - r o (2) impedance output with buffer off ---15k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on -0.2 --v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.7 v dac_out max (2) higher dac_out voltage with buffer on --- v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off --0.5-mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --- v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) --170240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs - - 50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs docid028094 rev 5 117/142 stm32f410x8/b electrical characteristics 118 i dda (4) dac dc vdda current consumption in quiescent mode (3) - - 280 380 a with no load, middle code (0x800) on the inputs - - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code- 1lsb) - - - 0.5 lsb given for the dac in 10-bit configuration. ---2 lsb given for the dac in 12-bit configuration. inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) ---1lsb given for the dac in 10-bit configuration. ---4lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) ---10mv given for the dac in 12-bit configuration ---3lsb given for the dac in 10-bit at v ref+ = 3.6 v - - - 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - - 0.5 % given for the dac in 12-bit configuration t settling ( 4) total harmonic distortion buffer on --36s c load 50 pf, r load 5 k thd (4) -----db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) ---1 ms/ s c load 50 pf, r load 5 k table 77. dac characteristics (continued) symbol parameter conditions min typ max unit comments electrical characteristics stm32f410x8/b 118/142 docid028094 rev 5 figure 40. 12-bit buffered/non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.25 rtc characteristics t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) --6.510s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - - - ?67 - 40 db no r load , c load = 50 pf 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.15.2: internal reset off ). 2. guaranteed by design. 3. the quiescent mode corresponds to a state where the dac maintains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed based on test during characterization. table 77. dac characteristics (continued) symbol parameter conditions min typ max unit comments % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' d l g table 78. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4- docid028094 rev 5 119/142 stm32f410x8/b package information 139 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 wlcsp36 pac kage information figure 41. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. % d o o $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ( ' ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ h ) * h h % d o o $ e d o o o r f d w l r q h $ % x p s v l g h h h h = ) u r q w y l h z $ ) b 0 ( b 9 ) $ $ e $ e e e = f f f g g g = ; < = d d d ; = $ package information stm32f410x8/b 120/142 docid028094 rev 5 figure 42. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package recommended footprint table 79. wlcsp36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.170 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 2.518 2.553 2.588 0.1012 0.1026 0.1039 e 2.544 2.579 2.614 0.1050 0.1064 0.1078 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - f - 0.2765 - - 0.0119 - g - 0.2895 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 $ ) b ) 3 b 9 ' s d g ' v p docid028094 rev 5 121/142 stm32f410x8/b package information 139 wlcsp36 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 43. wlcsp36 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 80. wlcsp36 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.250 mm stencil thickness 0.100 mm 0 6 y 9 ) % : : < 5 3 u r g x f w l g h q w l i l f d w l r q % d o o l g h q w l i l h u ' d w h f r g h 5 h y l v l r q f r g h package information stm32f410x8/b 122/142 docid028094 rev 5 7.2 ufqfpn48 package information figure 44. ufqfpn48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. $ % b 0 ( b 9 ' 3 l q l g h q w l i l h u o d v h u p d u n l q j d u h d ( ( ' < ' ( ( [ s r v h g s d g d u h d = ' h w d l o = 5 w \ s / & [ ? s l q f r u q h u $ 6 h d w l q j s o d q h $ e h g g g ' h w d l o < 7 docid028094 rev 5 123/142 stm32f410x8/b package information 139 figure 45. ufqfpn48 recommended footprint 1. dimensions are in millimeters. table 81. ufqfpn48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. ! " ? & 0 ? 6 package information stm32f410x8/b 124/142 docid028094 rev 5 ufqfpn48 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 46. ufqfpn48 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) & % 8 < : : 5 3 l q l g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 5 h y l v l r q f r g h docid028094 rev 5 125/142 stm32f410x8/b package information 139 7.3 lqfp48 package information figure 47. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information stm32f410x8/b 126/142 docid028094 rev 5 table 82. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 docid028094 rev 5 127/142 stm32f410x8/b package information 139 figure 48. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. a i d package information stm32f410x8/b 128/142 docid028094 rev 5 lqfp48 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 49. lqfp48 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 6 7 0 ) & 8 0 6 y 9 3 l q l q g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 5 h y l v l r q f r g h $ < : : docid028094 rev 5 129/142 stm32f410x8/b package information 139 7.4 lqfp64 package information figure 50. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package information stm32f410x8/b 130/142 docid028094 rev 5 figure 51. lqfp64 recommended footprint 1. dimensions are in millimeters. table 83. lqfp64 - 64-pin, 10 x 10 mm lo w-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits. docid028094 rev 5 131/142 stm32f410x8/b package information 139 lqfp64 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 52. lqfp64 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 ) 5 % 7 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 3 l q l g h q w l i l h u 5 package information stm32f410x8/b 132/142 docid028094 rev 5 7.5 ufbga64 package information figure 53. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline 1. drawing is not to scale. table 84. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0 .0020 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 a3 0.080 0.130 0.180 0.0031 0.0051 0.0071 a4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - $ b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' + ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d $ docid028094 rev 5 133/142 stm32f410x8/b package information 139 figure 54. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint f 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 85. ufbga64 recommended pcb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.280 mm dsm 0.370 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.280 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.100 mm table 84. ufbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 $ b ) 3 b 9 ' s d g ' v p package information stm32f410x8/b 134/142 docid028094 rev 5 ufbga64 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 55. ufbga64 marking examp le (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. ) % $ < : : 0 6 y 9 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < h d u z h h n % d o o $ 5 h y l v l r q f r g h docid028094 rev 5 135/142 stm32f410x8/b package information 139 7.6 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 15: general operati ng conditions on page 53 . the maximum chip-junction temperature, t j max., in degrees cels ius, may be calculated using the following equation: t j max = t a max + (pd max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? pd max is the sum of p int max and p i/o max (pd max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.6.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 86. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp48 55 c/w thermal resistance junction-ambient lqfp64 46 thermal resistance junction-ambient ufqfpn48 33 thermal resistance junction-ambient wlcsp36 61 thermal resistance junction-ambient ufbga64 79 part numbering stm32f410x8/b 136/142 docid028094 rev 5 8 part numbering table 87. ordering information scheme example: stm32 f 410 c b y 6 tr device family stm32 = arm ? -based 32-bit microcontroller product type f = general-purpose device subfamily 410 = 410 line pin count t = 36 pins c = 48 pins r = 64 pins flash memory size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package i = ufbga t = lqfp u = ufqfpn y = wlcsp temperature range 6 = industrial temperature range, - 40 to 85 c 3 = industrial temperature range, - 40 to 125 c packing tr = tape and reel no character = tray or tube docid028094 rev 5 137/142 stm32f410x8/b recommendations when using the internal reset off 139 appendix a recommendations wh en using the internal reset off when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on-reset (por)/power- down reset (pdr) circuitry is disabled. ? the brownout reset (bro) circuitry must be disabled. by default bor is off. ? the embedded programmable voltage detector (pvd) is disabled. ? vbat functionality is no more available and vbat pin should be connected to vdd. a.1 operating conditions table 88. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait state (f flashmax ) maximum flash memory access frequency with no wait states (1) (2) 1. applicable only when the code is ex ecuted from flash memory. when t he code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash me mory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. i/o operation possible flash memory operations v dd = 1.7 to 2.1 v (3) 3. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 3.15.1: internal reset on ). conversion time up to 1.2 msps 20 mhz (4) 4. prefetch is not available. refer to an3430 applicat ion note for details on how to adjust performance and power. 100 mhz with 6 wait states no i/o compensation 8-bit erase and program operations only application block diagrams stm32f410x8/b 138/142 docid028094 rev 5 appendix b application block diagrams b.1 sensor hub application example figure 56. sensor hub application example 1 figure 57. sensor hub application example 2 0 6 y 9 $ f f h o h u r p h w h u * \ u r v f r s h 0 d j q h w r p h w h u 3 u h v v x u h $ p e l h q w o l j k w 3 u r [ l p l w \ 6 3 , 7 h p s h u d w x u h k x p l g l w \ 6 & / 6 ' $ 3 % 3 $ 6 & . 0 , 6 2 3 % 3 $ 7 ; 5 ; 3 $ 3 $ 8 $ 5 7 , & $ ' & 3 & n + ] r v f l o o d w r u 6 : ' , 2 3 $ 3 $ - 7 $ * 3 ' 5 b 2 1 9 ' ' * 3 , 2 [ * 3 , 2 v % 2 2 7 n 5 6 7 0 ) [ % : / & 6 3 s d f n d j h + 2 6 7 3 % 3 & 1 5 6 7 6 : & / . 3 $ 1 6 6 0 2 6 , 3 % 3 % 6 : 2 0 6 y 9 $ f f h o h u r p h w h u * \ u r v f r s h 0 d j q h w r p h w h u 3 u h v v x u h $ p e l h q w o l j k w 3 u r [ l p l w \ 7 h p s h u d w x u h k x p l g l w \ 6 & / 6 ' $ 3 % 3 $ 7 ; 5 ; 3 $ 3 $ 8 $ 5 7 , & $ ' & 3 & n + ] r v f l o o d w r u 3 ' 5 b 2 1 9 ' ' * 3 , 2 [ * 3 , 2 v % 2 2 7 n 5 6 7 0 ) [ % : / & 6 3 s d f n d j h 3 % 3 & 6 3 , 6 & . 3 $ 3 % 0 l f u r s k r q h 0 , 6 2 0 + ] , & ) 0 3 $ 6 & / 6 ' $ 3 % + 2 6 7 1 5 6 7 , 1 3 % / r z s r z h u w l p h u 2 8 7 3 % 6 : ' , 2 3 $ 3 $ - 7 $ * 6 : & / . docid028094 rev 5 139/142 stm32f410x8/b application block diagrams 139 b.2 batch acquisition mode (bam) example data is transferred thro ugh the dma from interfaces into the internal sram while the rest of the mcu is set in low power mode. ? code execution from ram before switching off the flash. ? flash is set in power down and flash interface (art accelerator?) clock is stopped. ? the clocks are enabled only for the required interfaces. ? mcu core is set in sleep mode (core clock stopped waitin g for interrupt). ? only the needed dma channels are enabled and running. figure 58. batch acquisition mode (bam) example 0 6 y 9 $ f f h o h u r p h w h u * \ u r v f r s h 0 d j q h w r p h w h u 3 u h v v x u h $ p e l h q w o l j k w 3 u r [ l p l w \ 0 l f u r s k r q h 0 + ] , & ) 0 7 h p s h u d w x u h k x p l g l w \ 6 3 , 6 & / 6 ' $ 3 % 6 & . 0 , 6 2 3 $ 6 & / 6 ' $ 3 % 3 $ 7 ; 5 ; 3 $ 3 $ 8 $ 5 7 , & $ ' & 3 & n + ] r v f l o o d w r u 6 : ' , 2 3 $ 3 $ - 7 $ * 3 ' 5 b 2 1 9 ' ' * 3 , 2 [ * 3 , 2 v % 2 2 7 n 5 6 7 0 ) [ % : / & 6 3 s d f n d j h + 2 6 7 3 % 3 $ 3 % 3 & 1 5 6 7 6 : & / . , 1 3 % 3 % / r z s r z h u w l p h u 2 8 7 & r u w h [ ? 0 f r u h 0 + ] ) 3 8 0 3 8 . % ) o d v k p h p r u \ $ 5 7 $ f f h o h u d w r u ? . % 5 $ 0 ' 0 $ / r z s r z h u e o r f n v revision history stm32f410x8/b 140/142 docid028094 rev 5 revision history table 89. document revision history date revision changes 28-sep-2015 1 initial release. 07-dec-2015 2 junction temperature range changed to ?40 to + 110 c for wlcsp49 package. updated figure 7: ufqfpn48 pinout . 10-aug-2016 3 updated: ? table 2: stm32f410x8/b features and peripheral counts ? table 9: stm32f410x8/b pin definitions ? table 14: thermal characteristics ? table 15: general operating conditions ? table 20: embedded reset and power control block characteristics ? tables from table 21: typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - vdd = 1.7 v to table 34: typical and maximum current consumptions in vbat mode (lse and rtc on, lse low- drive mode) ? table 42: hsi oscillator characteristics ? table 43: lsi oscillator characteristics ? table 49: flash memory endurance and data retention ? table 52: esd absolute maximum ratings ? table 55: i/o static characteristics ? table 66: adc characteristics ? table 75: embedded internal reference voltage ? table 77: dac characteristics ? table 87: ordering information scheme ? figure 16: typical vbat current consumption (lse and rtc on/lse oscillator in ?low power? mode selection ? section 7: package information added: ? figure 5: lqfp48 pinout ? figure 8: ufbga64 pinout ? figure 49: lqfp48 marking example (package top view) ? figure 55: ufbga64 marking example (package top view) docid028094 rev 5 141/142 stm32f410x8/b revision history 141 06-mar-2017 4 updated: ? features ? section 3.20: timers and watchdogs ? table 9: stm32f410x8/b pin definitions ? table 21: typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - vdd = 1.7 v ? table 22: typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - vdd = 3.6 v ? table 24: typical and maximum current consumption in run mode, code with data processing (art accelerator enab led except prefetch) running from flash memory - vdd = 3.6 v ? table 28: typical and maximum current consumption in sleep mode - vdd = 3.6 v ? table 31: typical and maximum current consumption in stop mode - vdd=3.6 v ? table 34: typical and maximum current consumptions in vbat mode (lse and rtc on, lse low- drive mode) 04-apr-2017 5 the maximum current consumption at 30 c has been redefined to be in line with the actual silicon performance. for a typi cal customer application the impact on the average current consumption will be insignificant. updated: ? table 21: typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - vdd = 1.7 v ? table 22: typical and maximum current consumption, code with data processing (art accelerator disabled) running from sram - vdd = 3.6 v ? table 23: typical and maximum current consumption in run mode, code with data processing (art accelerator enab led except prefetch) running from flash memory- vdd = 1.7 v ? table 24: typical and maximum current consumption in run mode, code with data processing (art accelerator enab led except prefetch) running from flash memory - vdd = 3.6 v ? table 25: typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - vdd = 3.6 v ? table 26: typical and maximum current consumption in run mode, code with data processing (art accelerator disabled) running from flash memory - vdd = 1.7 v ? table 27: typical and maximum current consumption in run mode, code with data processing (art accelerator enabled with prefetch) running from flash memory - vdd = 3.6 v ? table 37: low-power mode wakeup timings ? figure 30: i2c bus ac waveforms and measurement circuit ? figure 31: fmpi2c timing diagram and measurement circuit table 89. document revision history (continued) date revision changes stm32f410x8/b 142/142 docid028094 rev 5 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved |
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